From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Thu, 18 Jul 2019 19:26:59 +0000 (-0700)
Subject: Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv... 
X-Git-Tag: v5.4-rc1~512
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0570bc8b7c9b41deba6f61ac218922e7168ad648;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'riscv/for-v5.3-rc1' of git://git./linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley:

 - Hugepage support

 - "Image" header support for RISC-V kernel binaries, compatible with
   the current ARM64 "Image" header

 - Initial page table setup now split into two stages

 - CONFIG_SOC support (starting with SiFive SoCs)

 - Avoid reserving memory between RAM start and the kernel in
   setup_bootmem()

 - Enable high-res timers and dynamic tick in the RV64 defconfig

 - Remove long-deprecated gate area stubs

 - MAINTAINERS updates to switch to the newly-created shared RISC-V git
   tree, and to fix a get_maintainers.pl issue for patches involving
   SiFive E-mail addresses

Also, one integration fix to resolve a build problem introduced during
in the v5.3-rc1 merge window:

 - Fix build break after macro-to-function conversion in
   asm-generic/cacheflush.h

* tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: fix build break after macro-to-function conversion in generic cacheflush.h
  RISC-V: Add an Image header that boot loader can parse.
  RISC-V: Setup initial page tables in two stages
  riscv: remove free_initrd_mem
  riscv: ccache: Remove unused variable
  riscv: Introduce huge page support for 32/64bit kernel
  x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig
  RISC-V: Fix memory reservation in setup_bootmem()
  riscv: defconfig: enable SOC_SIFIVE
  riscv: select SiFive platform drivers with SOC_SIFIVE
  arch: riscv: add config option for building SiFive's SoC resource
  riscv: Remove gate area stubs
  MAINTAINERS: change the arch/riscv git tree to the new shared tree
  MAINTAINERS: don't automatically patches involving SiFive to the linux-riscv list
  RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS
---

0570bc8b7c9b41deba6f61ac218922e7168ad648
diff --cc arch/riscv/Kconfig
index 13a1c0d,a7252b4..59a4727
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@@ -51,7 -50,8 +51,9 @@@ config RISC
  	select ARCH_HAS_PTE_SPECIAL
  	select ARCH_HAS_MMIOWB
  	select HAVE_EBPF_JIT if 64BIT
 +	select EDAC_SUPPORT
+ 	select ARCH_HAS_GIGANTIC_PAGE
+ 	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
  
  config MMU
  	def_bool y