From: Rajan Vaja Date: Mon, 2 Mar 2020 21:50:40 +0000 (-0800) Subject: clk: zynqmp: Limit bestdiv with maxdiv X-Git-Tag: v5.10.7~2373^2~7^4~6 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0541e0217ac8daef32650ba8477ff0a55f9a94b1;p=platform%2Fkernel%2Flinux-rpi.git clk: zynqmp: Limit bestdiv with maxdiv Clock divider value should not be greater than maximum divider value. So use minimum of best divider or maximum divider value. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Link: https://lkml.kernel.org/r/1583185843-20707-2-git-send-email-jolly.shah@xilinx.com Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 4be2cc7..5c41ddb 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -197,6 +197,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) bestdiv = rate % *prate ? 1 : bestdiv; + + bestdiv = min_t(u32, bestdiv, divider->max_div); *prate = rate * bestdiv; return rate;