From: Jeff Law Date: Mon, 23 Feb 1998 17:35:44 +0000 (+0000) Subject: * gas/mips/vr5400.s: Use absolute expression for performance X-Git-Tag: gdb-4_18~3220 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0504414dc9a4b7803c014b6257ed9adf2d86db6b;p=platform%2Fupstream%2Fbinutils.git * gas/mips/vr5400.s: Use absolute expression for performance register number. * gas/mips/vr5400.d: Corresponding changes. * gas/mips/r5900.s: Use absolute expression for performance register number. * gas/mips/r5900.d: Corresponding changes. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 733da0c..3eeb4bf 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -3,6 +3,7 @@ Mon Feb 23 10:31:05 1998 Jeffrey A Law (law@cygnus.com) * gas/mips/vr5400.s: Use absolute expression for performance register number. + * gas/mips/vr5400.d: Corresponding changes. end-sanitize-vr5400 start-sanitize-r5900 @@ -10,6 +11,7 @@ Mon Feb 23 10:31:05 1998 Jeffrey A Law (law@cygnus.com) * gas/mips/r5900.s: Use absolute expression for performance register number. + * gas/mips/r5900.d: Corresponding changes. Fri Feb 20 01:29:16 1998 Jeffrey A Law (law@cygnus.com) diff --git a/gas/testsuite/gas/mips/vr5400.d b/gas/testsuite/gas/mips/vr5400.d new file mode 100644 index 0000000..af48dd3 --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400.d @@ -0,0 +1,127 @@ +#objdump: -dr --prefix-addresses -mmips:5400 +#name: MIPS VR5400 +#as: -mcpu=vr5400 + +# Test the VR5400 macros. + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 mul \$a0,\$a1,\$a2 +0+0004 mulu \$a0,\$a1,\$a2 +0+0008 mulhi \$a0,\$a1,\$a2 +0+000c mulhiu \$a0,\$a1,\$a2 +0+0010 muls \$a0,\$a1,\$a2 +0+0014 mulsu \$a0,\$a1,\$a2 +0+0018 mulshi \$a0,\$a1,\$a2 +0+001c mulshiu \$a0,\$a1,\$a2 +0+0020 macc \$a0,\$a1,\$a2 +0+0024 maccu \$a0,\$a1,\$a2 +0+0028 macchi \$a0,\$a1,\$a2 +0+002c macchiu \$a0,\$a1,\$a2 +0+0030 msac \$a0,\$a1,\$a2 +0+0034 msacu \$a0,\$a1,\$a2 +0+0038 msachi \$a0,\$a1,\$a2 +0+003c msachiu \$a0,\$a1,\$a2 +0+0040 ror \$a0,\$a1,0x19 +0+0044 rorv \$a0,\$a1,\$a2 +0+0048 dror \$a0,\$a1,0x19 +0+004c dror32 \$a0,\$a1,0x19 +0+0050 dror32 \$a0,\$a1,0x19 +0+0054 drorv \$a0,\$a1,\$a2 +0+0058 dbreak +0+005c dret +0+0060 mfdr \$v1,\$3 +0+0064 mtdr \$v1,\$3 +0+0068 mfpc \$a0,1 +0+006c mfps \$a0,1 +0+0070 mtpc \$a0,1 +0+0074 mtps \$a0,1 +0+0078 add\.ob \$f0,\$f1,\$f2 +0+007c add\.ob \$f3,\$f4,\$f6\[2\] +0+0080 add\.ob \$f6,\$f5,0xf +0+0084 add\.ob \$f3,\$f7,0x1f +0+0088 and\.ob \$f0,\$f1,\$f2 +0+008c and\.ob \$f3,\$f4,\$f6\[2\] +0+0090 and\.ob \$f6,\$f5,0xf +0+0094 and\.ob \$f3,\$f7,0x1f +0+0098 c\.eq\.ob \$f0,\$f2 +0+009c c\.eq\.ob \$f3,\$f6\[2\] +0+00a0 c\.eq\.ob \$f6,0xf +0+00a4 c\.eq\.ob \$f3,0x1f +0+00a8 c\.le\.ob \$f0,\$f2 +0+00ac c\.le\.ob \$f3,\$f6\[2\] +0+00b0 c\.le\.ob \$f6,0xf +0+00b4 c\.le\.ob \$f3,0x1f +0+00b8 c\.lt\.ob \$f0,\$f2 +0+00bc c\.lt\.ob \$f3,\$f6\[2\] +0+00c0 c\.lt\.ob \$f6,0xf +0+00c4 c\.lt\.ob \$f3,0x1f +0+00c8 max\.ob \$f0,\$f1,\$f2 +0+00cc max\.ob \$f3,\$f4,\$f6\[2\] +0+00d0 max\.ob \$f6,\$f5,0xf +0+00d4 max\.ob \$f3,\$f7,0x1f +0+00d8 min\.ob \$f0,\$f1,\$f2 +0+00dc min\.ob \$f3,\$f4,\$f6\[2\] +0+00e0 min\.ob \$f6,\$f5,0xf +0+00e4 min\.ob \$f3,\$f7,0x1f +0+00e8 mul\.ob \$f0,\$f1,\$f2 +0+00ec mul\.ob \$f3,\$f4,\$f6\[2\] +0+00f0 mul\.ob \$f6,\$f5,0xf +0+00f4 mul\.ob \$f3,\$f7,0x1f +0+00f8 mula\.ob \$f0,\$f2 +0+00fc mula\.ob \$f3,\$f6\[2\] +0+0100 mula\.ob \$f6,0xf +0+0104 mula\.ob \$f3,0x1f +0+0108 mull\.ob \$f0,\$f2 +0+010c mull\.ob \$f3,\$f6\[2\] +0+0110 mull\.ob \$f6,0xf +0+0114 mull\.ob \$f3,0x1f +0+0118 muls\.ob \$f0,\$f2 +0+011c muls\.ob \$f3,\$f6\[2\] +0+0120 muls\.ob \$f6,0xf +0+0124 muls\.ob \$f3,0x1f +0+0128 mulsl\.ob \$f0,\$f2 +0+012c mulsl\.ob \$f3,\$f6\[2\] +0+0130 mulsl\.ob \$f6,0xf +0+0134 mulsl\.ob \$f3,0x1f +0+0138 nor\.ob \$f0,\$f1,\$f2 +0+013c nor\.ob \$f3,\$f4,\$f6\[2\] +0+0140 nor\.ob \$f6,\$f5,0xf +0+0144 nor\.ob \$f3,\$f7,0x1f +0+0148 or\.ob \$f0,\$f1,\$f2 +0+014c or\.ob \$f3,\$f4,\$f6\[2\] +0+0150 or\.ob \$f6,\$f5,0xf +0+0154 or\.ob \$f3,\$f7,0x1f +0+0158 pickf\.ob \$f0,\$f1,\$f2 +0+015c pickf\.ob \$f3,\$f4,\$f6\[2\] +0+0160 pickf\.ob \$f6,\$f5,0xf +0+0164 pickf\.ob \$f3,\$f7,0x1f +0+0168 pickt\.ob \$f0,\$f1,\$f2 +0+016c pickt\.ob \$f3,\$f4,\$f6\[2\] +0+0170 pickt\.ob \$f6,\$f5,0xf +0+0174 pickt\.ob \$f3,\$f7,0x1f +0+0178 sub\.ob \$f0,\$f1,\$f2 +0+017c sub\.ob \$f3,\$f4,\$f6\[2\] +0+0180 sub\.ob \$f6,\$f5,0xf +0+0184 sub\.ob \$f3,\$f7,0x1f +0+0188 xor\.ob \$f0,\$f1,\$f2 +0+018c xor\.ob \$f3,\$f4,\$f6\[2\] +0+0190 xor\.ob \$f6,\$f5,0xf +0+0194 xor\.ob \$f3,\$f7,0x1f +0+0198 alni\.ob \$f1,\$f2,\$f3,5 +0+019c shfl\.mixh\.ob \$f1,\$f2,\$f3 +0+01a0 shfl\.mixl\.ob \$f1,\$f2,\$f3 +0+01a4 bc2tl 0+4324 +0+01a8 shfl\.pacl\.ob \$f1,\$f2,\$f3 +0+01ac sll\.ob \$f2,\$f4,\$f5\[3\] +0+01b0 sll\.ob \$f3,\$f6,0xe +0+01b4 srl\.ob \$f2,\$f4,\$f5\[3\] +0+01b8 srl\.ob \$f3,\$f6,0xe +0+01bc rzu\.ob \$f2,0xd +0+01c0 rach\.ob \$f2 +0+01c4 racl\.ob \$f2 +0+01c8 bc2f 0+04c8 +0+01cc wach\.ob \$f2 +0+01d0 wacl\.ob \$f2,\$f3 + ...