From: Samuel Pitoiset Date: Thu, 26 Nov 2020 06:46:11 +0000 (+0100) Subject: radv: disable WGP_MODE for NGG on GFX10.3 X-Git-Tag: upstream/21.0.0~2010 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=04ea3d65018ede109ba9a94f61bea3076eabf969;p=platform%2Fupstream%2Fmesa.git radv: disable WGP_MODE for NGG on GFX10.3 Ported from RadeonSI, reducing the CU mask probably broke WGP mode. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index ea9b944..cf0b3c3 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1039,8 +1039,12 @@ static void radv_postprocess_config(const struct radv_device *device, gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ } + /* Disable the WGP mode on gfx10.3 because it can hang. (it + * happened on VanGogh) Let's disable it on all chips that + * disable exactly 1 CU per SA for GS. + */ config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) | - S_00B228_WGP_MODE(1); + S_00B848_WGP_MODE(pdevice->rad_info.chip_class == GFX10); config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_LDS_SIZE(config_in->lds_size) | S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);