From: Vladimir Oltean Date: Tue, 27 Sep 2022 19:15:19 +0000 (+0300) Subject: net: dsa: felix: use DEFINE_RES_MEM_NAMED for resources X-Git-Tag: v6.1-rc5~319^2~68^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=044d447a801f2d0c03e153ef41835aebf66ca2d6;p=platform%2Fkernel%2Flinux-starfive.git net: dsa: felix: use DEFINE_RES_MEM_NAMED for resources Use less verbose resource definitions in vsc9959 and vsc9953. This also sets IORESOURCE_MEM in the constant array of resources, so we don't have to do this from felix_init_structs() - in fact, in the future, we may even support IORESOURCE_REG resources. Note that this macro takes start and length as argument, and we had start and end before. So transform end into length. While at it, sort the resources according to their offset. Signed-off-by: Vladimir Oltean Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index b7a66c1..6a7643c 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -1356,7 +1356,6 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) continue; memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); - res.flags = IORESOURCE_MEM; res.start += felix->switch_base; res.end += felix->switch_base; @@ -1393,7 +1392,6 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) } memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); - res.flags = IORESOURCE_MEM; res.start += felix->switch_base; res.end += felix->switch_base; diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index e465e3f..1872727 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -478,99 +478,32 @@ static const u32 *vsc9959_regmap[TARGET_MAX] = { /* Addresses are relative to the PCI device's base address */ static const struct resource vsc9959_target_io_res[TARGET_MAX] = { - [ANA] = { - .start = 0x0280000, - .end = 0x028ffff, - .name = "ana", - }, - [QS] = { - .start = 0x0080000, - .end = 0x00800ff, - .name = "qs", - }, - [QSYS] = { - .start = 0x0200000, - .end = 0x021ffff, - .name = "qsys", - }, - [REW] = { - .start = 0x0030000, - .end = 0x003ffff, - .name = "rew", - }, - [SYS] = { - .start = 0x0010000, - .end = 0x001ffff, - .name = "sys", - }, - [S0] = { - .start = 0x0040000, - .end = 0x00403ff, - .name = "s0", - }, - [S1] = { - .start = 0x0050000, - .end = 0x00503ff, - .name = "s1", - }, - [S2] = { - .start = 0x0060000, - .end = 0x00603ff, - .name = "s2", - }, - [PTP] = { - .start = 0x0090000, - .end = 0x00900cb, - .name = "ptp", - }, - [GCB] = { - .start = 0x0070000, - .end = 0x00701ff, - .name = "devcpu_gcb", - }, + [SYS] = DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), + [REW] = DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), + [S0] = DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), + [S1] = DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), + [S2] = DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), + [GCB] = DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), + [QS] = DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), + [PTP] = DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), + [QSYS] = DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), + [ANA] = DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), }; static const struct resource vsc9959_port_io_res[] = { - { - .start = 0x0100000, - .end = 0x010ffff, - .name = "port0", - }, - { - .start = 0x0110000, - .end = 0x011ffff, - .name = "port1", - }, - { - .start = 0x0120000, - .end = 0x012ffff, - .name = "port2", - }, - { - .start = 0x0130000, - .end = 0x013ffff, - .name = "port3", - }, - { - .start = 0x0140000, - .end = 0x014ffff, - .name = "port4", - }, - { - .start = 0x0150000, - .end = 0x015ffff, - .name = "port5", - }, + DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), + DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), + DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), + DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), + DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), + DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), }; /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an * SGMII/QSGMII MAC PCS can be found. */ -static const struct resource vsc9959_imdio_res = { - .start = 0x8030, - .end = 0x8040, - .name = "imdio", -}; +static const struct resource vsc9959_imdio_res = + DEFINE_RES_MEM_NAMED(0x8030, 0x8040, "imdio"); static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), @@ -1026,7 +959,6 @@ static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); memcpy(&res, &vsc9959_imdio_res, sizeof(res)); - res.flags = IORESOURCE_MEM; res.start += imdio_base; res.end += imdio_base; diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index e807db0..66237c4 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -459,109 +459,29 @@ static const u32 *vsc9953_regmap[TARGET_MAX] = { /* Addresses are relative to the device's base address */ static const struct resource vsc9953_target_io_res[TARGET_MAX] = { - [ANA] = { - .start = 0x0280000, - .end = 0x028ffff, - .name = "ana", - }, - [QS] = { - .start = 0x0080000, - .end = 0x00800ff, - .name = "qs", - }, - [QSYS] = { - .start = 0x0200000, - .end = 0x021ffff, - .name = "qsys", - }, - [REW] = { - .start = 0x0030000, - .end = 0x003ffff, - .name = "rew", - }, - [SYS] = { - .start = 0x0010000, - .end = 0x001ffff, - .name = "sys", - }, - [S0] = { - .start = 0x0040000, - .end = 0x00403ff, - .name = "s0", - }, - [S1] = { - .start = 0x0050000, - .end = 0x00503ff, - .name = "s1", - }, - [S2] = { - .start = 0x0060000, - .end = 0x00603ff, - .name = "s2", - }, - [PTP] = { - .start = 0x0090000, - .end = 0x00900cb, - .name = "ptp", - }, - [GCB] = { - .start = 0x0070000, - .end = 0x00701ff, - .name = "devcpu_gcb", - }, + [SYS] = DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), + [REW] = DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), + [S0] = DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), + [S1] = DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), + [S2] = DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), + [GCB] = DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), + [QS] = DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), + [PTP] = DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), + [QSYS] = DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), + [ANA] = DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), }; static const struct resource vsc9953_port_io_res[] = { - { - .start = 0x0100000, - .end = 0x010ffff, - .name = "port0", - }, - { - .start = 0x0110000, - .end = 0x011ffff, - .name = "port1", - }, - { - .start = 0x0120000, - .end = 0x012ffff, - .name = "port2", - }, - { - .start = 0x0130000, - .end = 0x013ffff, - .name = "port3", - }, - { - .start = 0x0140000, - .end = 0x014ffff, - .name = "port4", - }, - { - .start = 0x0150000, - .end = 0x015ffff, - .name = "port5", - }, - { - .start = 0x0160000, - .end = 0x016ffff, - .name = "port6", - }, - { - .start = 0x0170000, - .end = 0x017ffff, - .name = "port7", - }, - { - .start = 0x0180000, - .end = 0x018ffff, - .name = "port8", - }, - { - .start = 0x0190000, - .end = 0x019ffff, - .name = "port9", - }, + DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), + DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), + DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), + DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), + DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), + DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), + DEFINE_RES_MEM_NAMED(0x0160000, 0x0010000, "port6"), + DEFINE_RES_MEM_NAMED(0x0170000, 0x0010000, "port7"), + DEFINE_RES_MEM_NAMED(0x0180000, 0x0010000, "port8"), + DEFINE_RES_MEM_NAMED(0x0190000, 0x0010000, "port9"), }; static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {