From: Luís Marques <luismarques@lowrisc.org>
Date: Mon, 13 Jan 2020 15:33:07 +0000 (+0000)
Subject: [RISCV] Handle globals and block addresses in asm operands
X-Git-Tag: llvmorg-11-init~252
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=043c5eafa8789d76b06b93d157c928830c4d0814;p=platform%2Fupstream%2Fllvm.git

[RISCV] Handle globals and block addresses in asm operands

Summary: These seem to be the machine operand types currently needed by the
RISC-V target.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72275
---

diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 7247adf..60ea404 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -121,6 +121,14 @@ bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
   case MachineOperand::MO_Register:
     OS << RISCVInstPrinter::getRegisterName(MO.getReg());
     return false;
+  case MachineOperand::MO_GlobalAddress:
+    PrintSymbolOperand(MO, OS);
+    return false;
+  case MachineOperand::MO_BlockAddress: {
+    MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
+    Sym->print(OS, MAI);
+    return false;
+  }
   default:
     break;
   }
diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
index c5aa854..a16f127 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -78,7 +78,7 @@ define i32 @constraint_m2(i32* %a) nounwind {
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
-  %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
+  %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a)
   ret i32 %1
 }
 
@@ -249,4 +249,46 @@ define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
   ret i32 %1
 }
 
-; TODO: expend tests for more complex constraints, out of range immediates etc
+define void @operand_global() nounwind {
+; RV32I-LABEL: operand_global:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    .8byte gi
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: operand_global:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    .8byte gi
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+  tail call void asm sideeffect ".8byte $0", "i"(i32* @gi)
+  ret void
+}
+
+define void @operand_block_address() nounwind {
+; RV32I-LABEL: operand_block_address:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    j .Ltmp0
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:  .Ltmp0: # Block address taken
+; RV32I-NEXT:  # %bb.1: # %bb
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: operand_block_address:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    j .Ltmp0
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:  .Ltmp0: # Block address taken
+; RV64I-NEXT:  # %bb.1: # %bb
+; RV64I-NEXT:    ret
+  call void asm sideeffect "j $0", "i"(i8* blockaddress(@operand_block_address, %bb))
+  br label %bb
+bb:
+  ret void
+}
+
+; TODO: expand tests for more complex constraints, out of range immediates etc