From: Rajan Vaja Date: Mon, 28 Jun 2021 07:01:22 +0000 (-0700) Subject: clk: zynqmp: Handle divider specific read only flag X-Git-Tag: accepted/tizen/unified/20230118.172025~6866^2~11^5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=03aea91bbe06d4ffae8c22c9e1e6671a76fd6d5a;p=platform%2Fkernel%2Flinux-rpi.git clk: zynqmp: Handle divider specific read only flag Add support for divider specific read only CCF flag (CLK_DIVIDER_READ_ONLY). Signed-off-by: Rajan Vaja Link: https://lore.kernel.org/r/20210628070122.26217-5-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index c07423e..cb49281 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -256,6 +256,11 @@ static const struct clk_ops zynqmp_clk_divider_ops = { .set_rate = zynqmp_clk_divider_set_rate, }; +static const struct clk_ops zynqmp_clk_divider_ro_ops = { + .recalc_rate = zynqmp_clk_divider_recalc_rate, + .round_rate = zynqmp_clk_divider_round_rate, +}; + /** * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. * @clk_id: Id of clock @@ -334,7 +339,10 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, return ERR_PTR(-ENOMEM); init.name = name; - init.ops = &zynqmp_clk_divider_ops; + if (nodes->type_flag & CLK_DIVIDER_READ_ONLY) + init.ops = &zynqmp_clk_divider_ro_ops; + else + init.ops = &zynqmp_clk_divider_ops; init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);