From: Marek Szyprowski Date: Thu, 26 Apr 2018 13:18:54 +0000 (+0200) Subject: hack: arm64: exynos5433: use only ARCH TIMER X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=03242e5ba08f28879012e557715ec1a12dd3459c;p=platform%2Fkernel%2Flinux-exynos.git hack: arm64: exynos5433: use only ARCH TIMER Signed-off-by: Marek Szyprowski --- diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index a168c5608e81..aaa586788e72 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -298,6 +298,18 @@ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x5c000>; @@ -2529,17 +2541,6 @@ }; }; - timer: timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; }; #include "exynos5433-bus.dtsi" diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 78778062937b..e220d22afbc0 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -161,8 +161,12 @@ static inline u64 arch_counter_get_cntpct(void) static inline u64 arch_counter_get_cntvct(void) { + u64 cval; + isb(); - return arch_timer_reg_read_stable(cntvct_el0); + asm volatile("mrs %0, cntpct_el0" : "=r" (cval)); + + return cval; } static inline int arch_timer_arch_init(void) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 8383af15a759..9f2083974e10 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -497,7 +497,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) { int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; - pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); + pt_regs_write_reg(regs, rt, arch_counter_get_cntpct()); regs->pc += 4; } diff --git a/arch/arm64/kernel/vdso/gettimeofday.S b/arch/arm64/kernel/vdso/gettimeofday.S index 76320e920965..336b273a322a 100644 --- a/arch/arm64/kernel/vdso/gettimeofday.S +++ b/arch/arm64/kernel/vdso/gettimeofday.S @@ -66,7 +66,7 @@ x_tmp .req x8 .macro get_clock_shifted_nsec res, cycle_last, mult /* Read the virtual counter. */ isb - mrs x_tmp, cntvct_el0 + mrs x_tmp, cntpct_el0 /* Calculate cycle delta and convert to ns. */ sub \res, x_tmp, \cycle_last /* We can only guarantee 56 bits of precision. */ diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 63cdb8bc72b7..ea2f47e2f0cb 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -71,15 +71,13 @@ static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI]; static struct clock_event_device __percpu *arch_timer_evt; -static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI; +static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI; static bool arch_timer_c3stop; static bool arch_timer_mem_use_virtual; static bool arch_counter_suspend_stop; static bool vdso_default = true; static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); -static bool mct_enable = IS_ENABLED(CONFIG_CLKSRC_EXYNOS_MCT); - static int __init early_evtstrm_cfg(char *buf) { return strtobool(buf, &evtstrm_enable); @@ -776,7 +774,7 @@ static void arch_counter_set_user_access(void) if (arch_timer_this_cpu_has_cntvct_wa()) pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id()); else - cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; + cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN | ARCH_TIMER_USR_PCT_ACCESS_EN; arch_timer_set_cntkctl(cntkctl); } @@ -891,8 +889,7 @@ static void __init arch_counter_register(unsigned type) /* Register the CP15 based counter if we have one */ if (type & ARCH_TIMER_TYPE_CP15) { - if (IS_ENABLED(CONFIG_ARM64) || - arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) + if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) arch_timer_read_counter = arch_counter_get_cntpct; else arch_timer_read_counter = arch_counter_get_cntpct; @@ -1019,24 +1016,12 @@ static int __init arch_timer_register(void) goto out_unreg_notify; - if (mct_enable) { - /* - * FIXME: The arm64 architecture enables the arm_arch_timer always - * even if arm_arch_timer is not stable. When Exynos5433 uses the - * arm_arch_timer, it fails to enable/disble the secondary cpu. - * To fix the hotplug issue of secondary cpu, if Exynos's MCT timer - * is enabled, arm_arch_timer doesn't register the clockevent - * for Per-CPU. - */ - return 0; - } else { - /* Register and immediately configure the timer on the boot CPU */ - err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, - "clockevents/arm/arch_timer:starting", - arch_timer_starting_cpu, arch_timer_dying_cpu); - if (err) - goto out_unreg_cpupm; - } + /* Register and immediately configure the timer on the boot CPU */ + err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING, + "clockevents/arm/arch_timer:starting", + arch_timer_starting_cpu, arch_timer_dying_cpu); + if (err) + goto out_unreg_cpupm; return 0; @@ -1150,13 +1135,13 @@ static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void) { if (is_kernel_in_hyp_mode()) return ARCH_TIMER_HYP_PPI; - +/* if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) return ARCH_TIMER_VIRT_PPI; if (IS_ENABLED(CONFIG_ARM64)) return ARCH_TIMER_PHYS_NONSECURE_PPI; - +*/ return ARCH_TIMER_PHYS_SECURE_PPI; } diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 7a244b681876..9551f79abf18 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -237,7 +237,7 @@ static cycles_t exynos4_read_current_timer(void) static int __init exynos4_clocksource_init(void) { exynos4_mct_frc_start(); - +#if 0 #if defined(CONFIG_ARM) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate; @@ -248,7 +248,7 @@ static int __init exynos4_clocksource_init(void) panic("%s: can't register clocksource\n", mct_frc.name); sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); - +#endif return 0; } @@ -343,11 +343,12 @@ static struct irqaction mct_comp_event_irq = { static int exynos4_clockevent_init(void) { +#if 0 mct_comp_device.cpumask = cpumask_of(0); clockevents_config_and_register(&mct_comp_device, clk_rate, 0xf, 0xffffffff); setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); - +#endif return 0; } @@ -468,7 +469,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) evt->rating = 450; exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); - +#if 0 if (mct_int_type == MCT_INT_SPI) { if (evt->irq == -1) @@ -481,7 +482,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) } clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), 0xf, 0x7fffffff); - +#endif return 0; } @@ -492,6 +493,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) struct clock_event_device *evt = &mevt->evt; evt->set_state_shutdown(evt); +#if 0 if (mct_int_type == MCT_INT_SPI) { if (evt->irq != -1) disable_irq_nosync(evt->irq); @@ -499,6 +501,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) } else { disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); } +#endif return 0; } @@ -521,7 +524,7 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem * reg_base = base; if (!reg_base) panic("%s: unable to ioremap mct address space\n", __func__); - +#if 0 if (mct_int_type == MCT_INT_PPI) { err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], @@ -550,7 +553,7 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem * pcpu_mevt->evt.irq = mct_irq; } } - +#endif /* Install hotplug callbacks which configure the timer on this CPU */ err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, "clockevents/exynos4/mct_timer:starting",