From: Vinay Kumar Date: Tue, 27 Oct 2015 14:00:40 +0000 (+0000) Subject: Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when... X-Git-Tag: users/ARM/embedded-binutils-2_26-branch-2016q1~282 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=02f12cd4669463a1b2346145808213adeb303e2d;p=external%2Fbinutils.git Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when zero. PR binutils/19157 opcodes * rl78-decode.opc: Add 'a' print operator to mov instructions using stack pointer plus index addressing. * rl78-decode.c: Regenerate. tests * gas/rl78: New directory. * gas/rl78/rl78.exp: New test driver. * gas/rl78/pr19157.s: New test source file. * gas/rl78/pr19157.d: New test case. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 89d282f..df44690 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2015-10-27 Nick Clifton + + PR binutils/19157 + * gas/rl78: New directory. + * gas/rl78/rl78.exp: New test driver. + * gas/rl78/pr19157.s: New test source file. + * gas/rl78/pr19157.d: New test case. + 2015-10-22 Nick Clifton * gas/msp430/errata_fixes.s: New test source file. diff --git a/gas/testsuite/gas/rl78/pr19157.d b/gas/testsuite/gas/rl78/pr19157.d new file mode 100644 index 0000000..9bbbc10 --- /dev/null +++ b/gas/testsuite/gas/rl78/pr19157.d @@ -0,0 +1,15 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: PR19157: RL78: zero offset omitted + +.*: +file format .*rl78.* + +Disassembly of section .text: +0x0+000 88 00[ ]+mov[ ]+a, \[sp\+0\] +0x0+002 88 00[ ]+mov[ ]+a, \[sp\+0\] +0x0+004 88 01[ ]+mov[ ]+a, \[sp\+1\] +0x0+006 a8 00[ ]+movw[ ]+ax, \[sp\+0\] +0x0+008 a8 00[ ]+movw[ ]+ax, \[sp\+0\] +0x0+00a a8 02[ ]+movw[ ]+ax, \[sp\+2\] +0x0+00c c8 00 09[ ]+mov[ ]+\[sp\+0\], #9 +0x0+00f c8 00 09[ ]+mov[ ]+\[sp\+0\], #9 +0x0+012 c8 01 09[ ]+mov[ ]+\[sp\+1\], #9 diff --git a/gas/testsuite/gas/rl78/pr19157.s b/gas/testsuite/gas/rl78/pr19157.s new file mode 100644 index 0000000..2da33b7 --- /dev/null +++ b/gas/testsuite/gas/rl78/pr19157.s @@ -0,0 +1,13 @@ + .text + + mov a, [sp] + mov a, [sp + 0] + mov a, [sp + 1] + movw ax, [sp] + movw ax, [sp + 0] + movw ax, [sp + 2] + mov [sp], # 9 + mov [sp + 0], # 9 + mov [sp + 1], # 9 + + .end diff --git a/gas/testsuite/gas/rl78/rl78.exp b/gas/testsuite/gas/rl78/rl78.exp new file mode 100644 index 0000000..9341981 --- /dev/null +++ b/gas/testsuite/gas/rl78/rl78.exp @@ -0,0 +1,23 @@ +# Copyright (C) 2015 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +# +# RL78 tests +# + +if [expr [istarget "rl78-*-*"]] then { + run_dump_test "pr19157" +} diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3bd728a..a2a9cd4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2015-10-27 Vinay Kumar + + PR binutils/19157 + * rl78-decode.opc: Add 'a' print operator to mov instructions + using stack pointer plus index addressing. + * rl78-decode.c: Regenerate. + 2015-10-14 Andreas Krebbel * s390-opc.c: Fix comment. diff --git a/opcodes/rl78-decode.c b/opcodes/rl78-decode.c index 97c203d..be78c6a 100644 --- a/opcodes/rl78-decode.c +++ b/opcodes/rl78-decode.c @@ -4331,14 +4331,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0x88: { - /** 1000 1000 mov %0, %e1 */ + /** 1000 1000 mov %0, %ea1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1000 1000 mov %0, %e1 */", + "/** 1000 1000 mov %0, %ea1 */", op[0]); } - SYNTAX("mov %0, %e1"); + SYNTAX("mov %0, %ea1"); #line 666 "rl78-decode.opc" ID(mov); DR(A); SM(SP, IMMU(1)); @@ -4476,14 +4476,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0x98: { - /** 1001 1000 mov %0, %1 */ + /** 1001 1000 mov %a0, %1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1001 1000 mov %0, %1 */", + "/** 1001 1000 mov %a0, %1 */", op[0]); } - SYNTAX("mov %0, %1"); + SYNTAX("mov %a0, %1"); #line 642 "rl78-decode.opc" ID(mov); DM(SP, IMMU(1)); SR(A); @@ -4683,14 +4683,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xa8: { - /** 1010 1000 movw %0, %1 */ + /** 1010 1000 movw %0, %a1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1010 1000 movw %0, %1 */", + "/** 1010 1000 movw %0, %a1 */", op[0]); } - SYNTAX("movw %0, %1"); + SYNTAX("movw %0, %a1"); #line 850 "rl78-decode.opc" ID(mov); W(); DR(AX); SM(SP, IMMU(1)); @@ -4889,14 +4889,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xb8: { - /** 1011 1000 movw %0, %1 */ + /** 1011 1000 movw %a0, %1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1011 1000 movw %0, %1 */", + "/** 1011 1000 movw %a0, %1 */", op[0]); } - SYNTAX("movw %0, %1"); + SYNTAX("movw %a0, %1"); #line 831 "rl78-decode.opc" ID(mov); W(); DM(SP, IMMU(1)); SR(AX); @@ -5053,14 +5053,14 @@ rl78_decode_opcode (unsigned long pc AU, break; case 0xc8: { - /** 1100 1000 mov %0, #%1 */ + /** 1100 1000 mov %a0, #%1 */ if (trace) { printf ("\033[33m%s\033[0m %02x\n", - "/** 1100 1000 mov %0, #%1 */", + "/** 1100 1000 mov %a0, #%1 */", op[0]); } - SYNTAX("mov %0, #%1"); + SYNTAX("mov %a0, #%1"); #line 639 "rl78-decode.opc" ID(mov); DM(SP, IMMU(1)); SC(IMMU(1)); diff --git a/opcodes/rl78-decode.opc b/opcodes/rl78-decode.opc index 6475b62..8bb8d09 100644 --- a/opcodes/rl78-decode.opc +++ b/opcodes/rl78-decode.opc @@ -635,10 +635,10 @@ rl78_decode_opcode (unsigned long pc AU, /** 0110 0001 1111 1001 mov %e0, %1 */ ID(mov); DM2(HL, C, 0); SR(A); -/** 1100 1000 mov %0, #%1 */ +/** 1100 1000 mov %a0, #%1 */ ID(mov); DM(SP, IMMU(1)); SC(IMMU(1)); -/** 1001 1000 mov %0, %1 */ +/** 1001 1000 mov %a0, %1 */ ID(mov); DM(SP, IMMU(1)); SR(A); /** 1000 1111 mov %0, %e!1 */ @@ -662,7 +662,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 0110 0001 1110 1001 mov %0, %e1 */ ID(mov); DR(A); SM2(HL, C, 0); -/** 1000 1000 mov %0, %e1 */ +/** 1000 1000 mov %0, %ea1 */ ID(mov); DR(A); SM(SP, IMMU(1)); /** 0101 0reg mov %0, #%1 */ @@ -827,7 +827,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1011 1100 movw %ea0, %1 */ ID(mov); W(); DM(HL, IMMU(1)); SR(AX); -/** 1011 1000 movw %0, %1 */ +/** 1011 1000 movw %a0, %1 */ ID(mov); W(); DM(SP, IMMU(1)); SR(AX); /** 1010 1111 movw %0, %e!1 */ @@ -846,7 +846,7 @@ rl78_decode_opcode (unsigned long pc AU, /** 1010 1100 movw %0, %ea1 */ ID(mov); W(); DR(AX); SM(HL, IMMU(1)); -/** 1010 1000 movw %0, %1 */ +/** 1010 1000 movw %0, %a1 */ ID(mov); W(); DR(AX); SM(SP, IMMU(1)); /** 0011 0rg0 movw %0, #%1 */