From: sgjesse@chromium.org <sgjesse@chromium.org@ce2b1a6d-e550-0410-aec6-3dcde31c8c00>
Date: Tue, 18 May 2010 06:38:42 +0000 (+0000)
Subject: ARM: Fix generating two ldr instructions in place of ldrd.
X-Git-Tag: upstream/4.7.83~21795
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=02ca5fd8b2560ab5b43db88042056ec2671aa1a8;p=platform%2Fupstream%2Fv8.git

ARM: Fix generating two ldr instructions in place of ldrd.

When ldrd is not available two ldr instructions are generated. This fixes these in the case where the register used in the memory operand is the same as the first register in the register pair receiving the values.

All tests now run on ARM with the flag --special-command="@ --noenable-vfp3". Running without VFP3 support in the simulator causes more ldrd instructions to be used, and the default build configuration does not utilize ldrd, but generated tow ldr instructions.
Review URL: http://codereview.chromium.org/2078013

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
---

diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index 1bcf99d..da32ce9 100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -1359,12 +1359,18 @@ void Assembler::ldrd(Register dst, const MemOperand& src, Condition cond) {
 #ifdef CAN_USE_ARMV7_INSTRUCTIONS
   addrmod3(cond | B7 | B6 | B4, dst, src);
 #else
-  ldr(dst, src, cond);
+  // Generate two ldr instructions if ldrd is not available.
   MemOperand src1(src);
   src1.set_offset(src1.offset() + 4);
   Register dst1(dst);
-  dst1.code_ = dst1.code_ + 1;
-  ldr(dst1, src1, cond);
+  dst1.set_code(dst1.code() + 1);
+  if (dst.is(src.rn())) {
+    ldr(dst1, src1, cond);
+    ldr(dst, src, cond);
+  } else {
+    ldr(dst, src, cond);
+    ldr(dst1, src1, cond);
+  }
 #endif
 }
 
@@ -1374,11 +1380,12 @@ void Assembler::strd(Register src, const MemOperand& dst, Condition cond) {
 #ifdef CAN_USE_ARMV7_INSTRUCTIONS
   addrmod3(cond | B7 | B6 | B5 | B4, src, dst);
 #else
-  str(src, dst, cond);
+  // Generate two str instructions if strd is not available.
   MemOperand dst1(dst);
   dst1.set_offset(dst1.offset() + 4);
   Register src1(src);
-  src1.code_ = src1.code_ + 1;
+  src1.set_code(src1.code() + 1);
+  str(src, dst, cond);
   str(src1, dst1, cond);
 #endif
 }
diff --git a/src/arm/assembler-arm.h b/src/arm/assembler-arm.h
index eb63b28..3d51183 100644
--- a/src/arm/assembler-arm.h
+++ b/src/arm/assembler-arm.h
@@ -80,6 +80,11 @@ struct Register {
     return 1 << code_;
   }
 
+  void set_code(int code) {
+    code_ = code;
+    ASSERT(is_valid());
+  }
+
   // Unfortunately we can't make this private in a struct.
   int code_;
 };
@@ -458,7 +463,8 @@ class MemOperand BASE_EMBEDDED {
       return offset_;
   }
 
-  Register rm() const {return rm_;}
+  Register rn() const { return rn_; }
+  Register rm() const { return rm_; }
 
  private:
   Register rn_;  // base