From: Samin Guo Date: Wed, 23 Aug 2023 02:43:54 +0000 (+0800) Subject: riscv: dts: starfive: jh7110: add dma-coherent for vpu/jpu X-Git-Tag: accepted/tizen/unified/x/20240220.145856~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=026ddfd6de4593ea84bd9f2ee674234b9dd66b9f;p=platform%2Fkernel%2Flinux-starfive.git riscv: dts: starfive: jh7110: add dma-coherent for vpu/jpu Use DMA-Coherent to avoid DIRECT_REMAP when allocating DMA buffers Signed-off-by: Samin Guo [sw0312.kim: cherry-pick the commit dfb44f0122ba from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel] Signed-off-by: Seung-Woo Kim Change-Id: Ia0d3955010e963c0fb635e10081c1a2ab31155d4 --- diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index c8c4f0be69c0..4ac5ca72f514 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1072,6 +1072,7 @@ jpu: jpu@13090000 { compatible = "starfive,jpu"; + dma-coherent; reg = <0x0 0x13090000 0x0 0x300>; interrupts = <14>; clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>, @@ -1090,6 +1091,7 @@ vpu_dec: vpu_dec@130A0000 { compatible = "starfive,vdec"; + dma-coherent; reg = <0x0 0x130A0000 0x0 0x10000>; interrupts = <13>; clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>, @@ -1113,6 +1115,7 @@ vpu_enc: vpu_enc@130B0000 { compatible = "starfive,venc"; + dma-coherent; reg = <0x0 0x130B0000 0x0 0x10000>; interrupts = <15>; clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>,