From: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Date: Fri, 2 Oct 2020 16:49:44 +0000 (-0400)
Subject: pan/bi: Drop if 0'd combine lowering
X-Git-Tag: upstream/21.0.0~4416
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=026a29506e4d103f54e3ccb1d7bc483b7369a093;p=platform%2Fupstream%2Fmesa.git

pan/bi: Drop if 0'd combine lowering

This is supposed to be optimized but actually just broken. When we look
at optimizing this later we'll probably want a more straightforward copy
prop pass instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
---

diff --git a/src/panfrost/bifrost/bi_lower_combine.c b/src/panfrost/bifrost/bi_lower_combine.c
index c8a06d4..189e2a6 100644
--- a/src/panfrost/bifrost/bi_lower_combine.c
+++ b/src/panfrost/bifrost/bi_lower_combine.c
@@ -84,24 +84,6 @@ bi_combine_sel16(bi_context *ctx, bi_instruction *parent, unsigned comp, unsigne
         bi_emit_before(ctx, parent, sel);
 }
 
-/* Gets the instruction generating a given source. Combine lowering is
- * accidentally O(n^2) right now because this function is O(n) instead of O(1).
- * If this pass is slow, this cost can be avoided in favour for better
- * bookkeeping. */
-
-#if 0
-static bi_instruction *
-bi_get_parent(bi_context *ctx, unsigned idx)
-{
-        bi_foreach_instr_global(ctx, ins) {
-                if (ins->dest == idx)
-                        return ins;
-        }
-
-        return NULL;
-}
-#endif
-
 /* Rewrites uses of an index. Again, this could be O(n) to the program but is
  * currently O(nc) to the program and number of combines, so the pass becomes
  * effectively O(n^2). Better bookkeeping would bring down to linear if that's
@@ -124,79 +106,6 @@ bi_rewrite_uses(bi_context *ctx,
         }
 }
 
-/* Checks if we have a nicely aligned vector prefix */
-
-#if 0
-static bool
-bi_is_aligned_vec32(bi_instruction *combine, unsigned s, bi_instruction *io,
-                unsigned *count)
-{
-        /* We only support prefixes */
-        if (s != 0)
-                return false;
-
-        if (!(bi_class_props[io->type] & BI_VECTOR))
-                return false;
-
-        if (nir_alu_type_get_type_size(combine->dest_type) != 32)
-                return false;
-
-        if (nir_alu_type_get_type_size(io->dest_type) != 32)
-                return false;
-
-        unsigned components = io->vector_channels;
-
-        /* Are we contiguous like that? */
-
-        for (unsigned i = 0; i < components; ++i) {
-                if (combine->src[i] != io->dest)
-                        return false;
-
-                if (combine->swizzle[i][0] != i)
-                        return false;
-        }
-
-        /* We're good to go */
-        *count = components;
-        return true;
-}
-
-/* Tries to lower a given source of a combine to an appropriate rewrite,
- * returning true if successful, and false with no changes otherwise. */
-
-static bool
-bi_lower_combine_src(bi_context *ctx, bi_instruction *ins, unsigned s, unsigned R,
-                unsigned *vec_count)
-{
-        unsigned src = ins->src[s];
-
-        /* We currently only handle SSA */
-
-        if (!src) return false;
-        if (src & (BIR_SPECIAL | PAN_IS_REG)) return false;
-
-        /* We are SSA. Lookup the generating instruction. */
-        unsigned bytes = nir_alu_type_get_type_size(ins->dest_type) / 8;
-
-        bi_instruction *parent = bi_get_parent(ctx, src,
-                         0xF << (ins->swizzle[s][0] * bytes));
-
-        if (!parent) return false;
-
-        /* We have a parent instuction, sanity check the typesize */
-        unsigned pbytes = nir_alu_type_get_type_size(parent->dest_type) / 8;
-        if (pbytes != bytes) return false;
-
-        bool scalar = parent->vector_channels != 0;
-        if (!(scalar || bi_is_aligned_vec(ins, s, parent, vec_count))) return false;
-
-        if (!bi_shift_mask(parent, bytes * s)) return false;
-        bi_rewrite_uses(ctx, parent->dest, 0, R, s);
-        parent->dest = R;
-        return true;
-}
-#endif
-
 /* Copies result of combine from the temp R to the instruction destination,
  * given a bitsize sz */
 
@@ -256,17 +165,6 @@ bi_lower_combine(bi_context *ctx, bi_block *block)
                         if (!ins->src[s])
                                 continue;
 
-#if 0
-                        unsigned vec_count = 0;
-
-                        if (bi_lower_combine_src(ctx, ins, s, R, &vec_count)) {
-                                /* Skip vectored sources */
-                                if (vec_count)
-                                        s += (vec_count - 1);
-                        } else {
-                                bi_insert_combine_mov(ctx, ins, s, R);
-                        }
-#endif
                         if (sz == 32)
                                 bi_combine_mov32(ctx, ins, s, R);
                         else if (sz == 16) {