From: Francisco Jerez <currojerez@riseup.net>
Date: Mon, 27 Jul 2015 15:51:01 +0000 (+0300)
Subject: i965/fs: Make the default builder 64-wide before entering the optimization loop.
X-Git-Tag: upstream/17.1.0~17294
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=02425d3ec2af6945a03583cadcaa5f3f330bbc0e;p=platform%2Fupstream%2Fmesa.git

i965/fs: Make the default builder 64-wide before entering the optimization loop.

Not a typo.  Replace the default builder with one of bogus width to
catch cases in which optimization passes assume that the default
dispatch width is good enough.  The execution controls of instructions
emitted during optimization should in general match the original code
that is being manipulated.  Many of the problems fixed in this series
were caught by the assertions introduced in this patch.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4947f24..565edeb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4671,9 +4671,11 @@ fs_visitor::optimize()
     * Ideally optimization passes wouldn't be part of the visitor so they
     * wouldn't have access to bld at all, but they do, so just in case some
     * pass forgets to ask for a location explicitly set it to NULL here to
-    * make it trip.
+    * make it trip.  The dispatch width is initialized to a bogus value to
+    * make sure that optimizations set the execution controls explicitly to
+    * match the code they are manipulating instead of relying on the defaults.
     */
-   bld = bld.at(NULL, NULL);
+   bld = fs_builder(this, 64);
 
    split_virtual_grfs();
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index 12653d0..34545ea 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -176,6 +176,8 @@ namespace brw {
       dst_reg
       vgrf(enum brw_reg_type type, unsigned n = 1) const
       {
+         assert(dispatch_width() <= 32);
+
          if (n > 0)
             return dst_reg(GRF, shader->alloc.allocate(
                               DIV_ROUND_UP(n * type_sz(type) * dispatch_width(),
@@ -342,6 +344,7 @@ namespace brw {
       instruction *
       emit(instruction *inst) const
       {
+         assert(inst->exec_size <= 32);
          assert(inst->exec_size == dispatch_width() ||
                 force_writemask_all);
          assert(_group == 0 || _group == 8);