From: Sam Parker Date: Thu, 12 Dec 2019 13:51:02 +0000 (+0000) Subject: [NFC][ARM] Add some test triples X-Git-Tag: llvmorg-11-init~2321 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=021b613cdc9091092e3429f36abdbe89a988681d;p=platform%2Fupstream%2Fllvm.git [NFC][ARM] Add some test triples Add thumb and thumb2 to a couple of the test files. --- diff --git a/llvm/test/CodeGen/ARM/mul_const.ll b/llvm/test/CodeGen/ARM/mul_const.ll index ada3d4e..adb615a 100644 --- a/llvm/test/CodeGen/ARM/mul_const.ll +++ b/llvm/test/CodeGen/ARM/mul_const.ll @@ -1,73 +1,203 @@ -; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM +; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s --check-prefix=THUMB2 +; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s --check-prefix=THUMB define i32 @t9(i32 %v) nounwind readnone { +; ARM-LABEL: t9: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: add r0, r0, r0, lsl #3 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: t9: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: add.w r0, r0, r0, lsl #3 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: t9: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #9 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: t9: -; CHECK: add r0, r0, r0, lsl #3 %0 = mul i32 %v, 9 ret i32 %0 } define i32 @t7(i32 %v) nounwind readnone { +; ARM-LABEL: t7: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: rsb r0, r0, r0, lsl #3 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: t7: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: rsb r0, r0, r0, lsl #3 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: t7: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #7 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: t7: -; CHECK: rsb r0, r0, r0, lsl #3 %0 = mul i32 %v, 7 ret i32 %0 } define i32 @t5(i32 %v) nounwind readnone { +; ARM-LABEL: t5: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: add r0, r0, r0, lsl #2 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: t5: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: add.w r0, r0, r0, lsl #2 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: t5: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #5 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: t5: -; CHECK: add r0, r0, r0, lsl #2 %0 = mul i32 %v, 5 ret i32 %0 } define i32 @t3(i32 %v) nounwind readnone { +; ARM-LABEL: t3: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: add r0, r0, r0, lsl #1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: t3: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: add.w r0, r0, r0, lsl #1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: t3: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #3 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: t3: -; CHECK: add r0, r0, r0, lsl #1 %0 = mul i32 %v, 3 ret i32 %0 } define i32 @t12288(i32 %v) nounwind readnone { +; ARM-LABEL: t12288: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: add r0, r0, r0, lsl #1 +; ARM-NEXT: lsl r0, r0, #12 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: t12288: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: add.w r0, r0, r0, lsl #1 +; THUMB2-NEXT: lsls r0, r0, #12 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: t12288: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #3 +; THUMB-NEXT: lsls r1, r1, #12 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: t12288: -; CHECK: add r0, r0, r0, lsl #1 -; CHECK: lsl{{.*}}#12 %0 = mul i32 %v, 12288 ret i32 %0 } define i32 @tn9(i32 %v) nounwind readnone { +; ARM-LABEL: tn9: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: add r0, r0, r0, lsl #3 +; ARM-NEXT: rsb r0, r0, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: tn9: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: add.w r0, r0, r0, lsl #3 +; THUMB2-NEXT: rsbs r0, r0, #0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: tn9: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #8 +; THUMB-NEXT: mvns r1, r1 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: tn9: -; CHECK: add r0, r0, r0, lsl #3 -; CHECK: rsb r0, r0, #0 %0 = mul i32 %v, -9 ret i32 %0 } define i32 @tn7(i32 %v) nounwind readnone { +; ARM-LABEL: tn7: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: sub r0, r0, r0, lsl #3 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: tn7: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: sub.w r0, r0, r0, lsl #3 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: tn7: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #6 +; THUMB-NEXT: mvns r1, r1 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: tn7: -; CHECK: sub r0, r0, r0, lsl #3 %0 = mul i32 %v, -7 ret i32 %0 } define i32 @tn5(i32 %v) nounwind readnone { +; ARM-LABEL: tn5: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: add r0, r0, r0, lsl #2 +; ARM-NEXT: rsb r0, r0, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: tn5: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: add.w r0, r0, r0, lsl #2 +; THUMB2-NEXT: rsbs r0, r0, #0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: tn5: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #4 +; THUMB-NEXT: mvns r1, r1 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: -; CHECK-LABEL: tn5: -; CHECK: add r0, r0, r0, lsl #2 -; CHECK: rsb r0, r0, #0 %0 = mul i32 %v, -5 ret i32 %0 } define i32 @tn3(i32 %v) nounwind readnone { +; ARM-LABEL: tn3: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: sub r0, r0, r0, lsl #2 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: tn3: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: sub.w r0, r0, r0, lsl #2 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: tn3: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: movs r1, #2 +; THUMB-NEXT: mvns r1, r1 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr entry: ; CHECK-LABEL: tn3: ; CHECK: sub r0, r0, r0, lsl #2 @@ -76,6 +206,27 @@ entry: } define i32 @tn12288(i32 %v) nounwind readnone { +; ARM-LABEL: tn12288: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: sub r0, r0, r0, lsl #2 +; ARM-NEXT: lsl r0, r0, #12 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: tn12288: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: sub.w r0, r0, r0, lsl #2 +; THUMB2-NEXT: lsls r0, r0, #12 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: tn12288: +; THUMB: @ %bb.0: @ %entry +; THUMB-NEXT: ldr r1, .LCPI9_0 +; THUMB-NEXT: muls r0, r1, r0 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .p2align 2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: .LCPI9_0: +; THUMB-NEXT: .long 4294955008 @ 0xffffd000 entry: ; CHECK-LABEL: tn12288: ; CHECK: sub r0, r0, r0, lsl #2 diff --git a/llvm/test/CodeGen/ARM/select_const.ll b/llvm/test/CodeGen/ARM/select_const.ll index 81b0db3..5004260 100644 --- a/llvm/test/CodeGen/ARM/select_const.ll +++ b/llvm/test/CodeGen/ARM/select_const.ll @@ -1,5 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=arm-eabi-unknown-unknown | FileCheck %s +; RUN: llc < %s -mtriple=arm-eabi-unknown-unknown | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv6t2-eabi-unknown-unknown | FileCheck %s --check-prefix=THUMB2 +; RUN: llc < %s -mtriple=thumb-eabi-unknown-unknown | FileCheck %s --check-prefix=THUMB ; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?). ; Test the zeroext/signext variants of each pattern to see if that makes a difference. @@ -7,30 +9,67 @@ ; select Cond, 0, 1 --> zext (!Cond) define i32 @select_0_or_1(i1 %cond) { -; CHECK-LABEL: select_0_or_1: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: bic r0, r1, r0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_1: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #1 +; ARM-NEXT: bic r0, r1, r0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_1: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: movs r1, #1 +; THUMB2-NEXT: bic.w r0, r1, r0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_1: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: bics r1, r0 +; THUMB-NEXT: movs r0, r1 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 0, i32 1 ret i32 %sel } define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_0_or_1_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: eor r0, r0, #1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_1_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: eor r0, r0, #1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_1_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: eor r0, r0, #1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_1_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: eors r0, r1 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 0, i32 1 ret i32 %sel } define i32 @select_0_or_1_signext(i1 signext %cond) { -; CHECK-LABEL: select_0_or_1_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: bic r0, r1, r0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_1_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #1 +; ARM-NEXT: bic r0, r1, r0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_1_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: movs r1, #1 +; THUMB2-NEXT: bic.w r0, r1, r0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_1_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: bics r1, r0 +; THUMB-NEXT: movs r0, r1 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 0, i32 1 ret i32 %sel } @@ -38,27 +77,57 @@ define i32 @select_0_or_1_signext(i1 signext %cond) { ; select Cond, 1, 0 --> zext (Cond) define i32 @select_1_or_0(i1 %cond) { -; CHECK-LABEL: select_1_or_0: -; CHECK: @ %bb.0: -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_1_or_0: +; ARM: @ %bb.0: +; ARM-NEXT: and r0, r0, #1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_1_or_0: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: and r0, r0, #1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_1_or_0: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: ands r0, r1 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel } define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_1_or_0_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_1_or_0_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_1_or_0_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_1_or_0_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel } define i32 @select_1_or_0_signext(i1 signext %cond) { -; CHECK-LABEL: select_1_or_0_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_1_or_0_signext: +; ARM: @ %bb.0: +; ARM-NEXT: and r0, r0, #1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_1_or_0_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: and r0, r0, #1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_1_or_0_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: ands r0, r1 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel } @@ -66,61 +135,131 @@ define i32 @select_1_or_0_signext(i1 signext %cond) { ; select Cond, 0, -1 --> sext (!Cond) define i32 @select_0_or_neg1(i1 %cond) { -; CHECK-LABEL: select_0_or_neg1: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: bic r0, r1, r0 -; CHECK-NEXT: rsb r0, r0, #0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_neg1: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #1 +; ARM-NEXT: bic r0, r1, r0 +; ARM-NEXT: rsb r0, r0, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_neg1: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: movs r1, #1 +; THUMB2-NEXT: bic.w r0, r1, r0 +; THUMB2-NEXT: rsbs r0, r0, #0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_neg1: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: bics r1, r0 +; THUMB-NEXT: rsbs r0, r1, #0 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 0, i32 -1 ret i32 %sel } define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_0_or_neg1_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: eor r0, r0, #1 -; CHECK-NEXT: rsb r0, r0, #0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_neg1_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: eor r0, r0, #1 +; ARM-NEXT: rsb r0, r0, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_neg1_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: eor r0, r0, #1 +; THUMB2-NEXT: rsbs r0, r0, #0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_neg1_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: eors r1, r0 +; THUMB-NEXT: rsbs r0, r1, #0 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 0, i32 -1 ret i32 %sel } define i32 @select_0_or_neg1_signext(i1 signext %cond) { -; CHECK-LABEL: select_0_or_neg1_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mvn r0, r0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_neg1_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mvn r0, r0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_neg1_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: mvns r0, r0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_neg1_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: mvns r0, r0 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 0, i32 -1 ret i32 %sel } define i32 @select_0_or_neg1_alt(i1 %cond) { -; CHECK-LABEL: select_0_or_neg1_alt: -; CHECK: @ %bb.0: -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: sub r0, r0, #1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_neg1_alt: +; ARM: @ %bb.0: +; ARM-NEXT: and r0, r0, #1 +; ARM-NEXT: sub r0, r0, #1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_neg1_alt: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: and r0, r0, #1 +; THUMB2-NEXT: subs r0, #1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_neg1_alt: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: ands r1, r0 +; THUMB-NEXT: subs r0, r1, #1 +; THUMB-NEXT: bx lr %z = zext i1 %cond to i32 %add = add i32 %z, -1 ret i32 %add } define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_0_or_neg1_alt_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: sub r0, r0, #1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_neg1_alt_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: sub r0, r0, #1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_neg1_alt_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: subs r0, #1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_neg1_alt_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: subs r0, r0, #1 +; THUMB-NEXT: bx lr %z = zext i1 %cond to i32 %add = add i32 %z, -1 ret i32 %add } define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) { -; CHECK-LABEL: select_0_or_neg1_alt_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mvn r0, r0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_0_or_neg1_alt_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mvn r0, r0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_0_or_neg1_alt_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: mvns r0, r0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_0_or_neg1_alt_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: mvns r0, r0 +; THUMB-NEXT: bx lr %z = zext i1 %cond to i32 %add = add i32 %z, -1 ret i32 %add @@ -129,28 +268,59 @@ define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) { ; select Cond, -1, 0 --> sext (Cond) define i32 @select_neg1_or_0(i1 %cond) { -; CHECK-LABEL: select_neg1_or_0: -; CHECK: @ %bb.0: -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsb r0, r0, #0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_neg1_or_0: +; ARM: @ %bb.0: +; ARM-NEXT: and r0, r0, #1 +; ARM-NEXT: rsb r0, r0, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_neg1_or_0: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: and r0, r0, #1 +; THUMB2-NEXT: rsbs r0, r0, #0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_neg1_or_0: +; THUMB: @ %bb.0: +; THUMB-NEXT: movs r1, #1 +; THUMB-NEXT: ands r1, r0 +; THUMB-NEXT: rsbs r0, r1, #0 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 -1, i32 0 ret i32 %sel } define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_neg1_or_0_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: rsb r0, r0, #0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_neg1_or_0_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: rsb r0, r0, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_neg1_or_0_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: rsbs r0, r0, #0 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_neg1_or_0_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: rsbs r0, r0, #0 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 -1, i32 0 ret i32 %sel } define i32 @select_neg1_or_0_signext(i1 signext %cond) { -; CHECK-LABEL: select_neg1_or_0_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_neg1_or_0_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_neg1_or_0_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_neg1_or_0_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 -1, i32 0 ret i32 %sel } @@ -158,37 +328,95 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; select Cond, C+1, C --> add (zext Cond), C define i32 @select_Cplus1_C(i1 %cond) { -; CHECK-LABEL: select_Cplus1_C: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #41 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: movne r1, #42 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_Cplus1_C: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #41 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: movne r1, #42 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_Cplus1_C: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r0, #41 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne r0, #42 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_Cplus1_C: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB15_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #41 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB15_2: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 42, i32 41 ret i32 %sel } define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_Cplus1_C_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #41 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: movne r1, #42 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_Cplus1_C_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #41 +; ARM-NEXT: cmp r0, #0 +; ARM-NEXT: movne r1, #42 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_Cplus1_C_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: movs r1, #41 +; THUMB2-NEXT: cmp r0, #0 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne r1, #42 +; THUMB2-NEXT: mov r0, r1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_Cplus1_C_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: cmp r0, #0 +; THUMB-NEXT: bne .LBB16_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #41 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB16_2: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 42, i32 41 ret i32 %sel } define i32 @select_Cplus1_C_signext(i1 signext %cond) { -; CHECK-LABEL: select_Cplus1_C_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #41 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: movne r1, #42 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_Cplus1_C_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #41 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: movne r1, #42 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_Cplus1_C_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r0, #41 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne r0, #42 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_Cplus1_C_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB17_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #41 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB17_2: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 42, i32 41 ret i32 %sel } @@ -196,37 +424,95 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) { ; select Cond, C, C+1 --> add (sext Cond), C define i32 @select_C_Cplus1(i1 %cond) { -; CHECK-LABEL: select_C_Cplus1: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #42 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: movne r1, #41 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_C_Cplus1: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #42 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: movne r1, #41 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_C_Cplus1: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r0, #42 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne r0, #41 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_C_Cplus1: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB18_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB18_2: +; THUMB-NEXT: movs r0, #41 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 41, i32 42 ret i32 %sel } define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_C_Cplus1_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #42 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: movne r1, #41 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_C_Cplus1_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #42 +; ARM-NEXT: cmp r0, #0 +; ARM-NEXT: movne r1, #41 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_C_Cplus1_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: movs r1, #42 +; THUMB2-NEXT: cmp r0, #0 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne r1, #41 +; THUMB2-NEXT: mov r0, r1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_C_Cplus1_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: cmp r0, #0 +; THUMB-NEXT: bne .LBB19_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB19_2: +; THUMB-NEXT: movs r0, #41 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 41, i32 42 ret i32 %sel } define i32 @select_C_Cplus1_signext(i1 signext %cond) { -; CHECK-LABEL: select_C_Cplus1_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #42 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: movne r1, #41 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_C_Cplus1_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #42 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: movne r1, #41 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_C_Cplus1_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r0, #42 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne r0, #41 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_C_Cplus1_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB20_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB20_2: +; THUMB-NEXT: movs r0, #41 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 41, i32 42 ret i32 %sel } @@ -235,40 +521,101 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) { ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2 define i32 @select_C1_C2(i1 %cond) { -; CHECK-LABEL: select_C1_C2: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #165 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: orr r1, r1, #256 -; CHECK-NEXT: moveq r1, #42 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_C1_C2: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #165 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: orr r1, r1, #256 +; ARM-NEXT: moveq r1, #42 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_C1_C2: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r0, #42 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movwne r0, #421 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_C1_C2: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB21_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB21_2: +; THUMB-NEXT: movs r0, #255 +; THUMB-NEXT: adds r0, #166 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 421, i32 42 ret i32 %sel } define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { -; CHECK-LABEL: select_C1_C2_zeroext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #165 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: orr r1, r1, #256 -; CHECK-NEXT: moveq r1, #42 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_C1_C2_zeroext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #165 +; ARM-NEXT: cmp r0, #0 +; ARM-NEXT: orr r1, r1, #256 +; ARM-NEXT: moveq r1, #42 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_C1_C2_zeroext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: movs r1, #42 +; THUMB2-NEXT: cmp r0, #0 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movwne r1, #421 +; THUMB2-NEXT: mov r0, r1 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_C1_C2_zeroext: +; THUMB: @ %bb.0: +; THUMB-NEXT: cmp r0, #0 +; THUMB-NEXT: bne .LBB22_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB22_2: +; THUMB-NEXT: movs r0, #255 +; THUMB-NEXT: adds r0, #166 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 421, i32 42 ret i32 %sel } define i32 @select_C1_C2_signext(i1 signext %cond) { -; CHECK-LABEL: select_C1_C2_signext: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #165 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: orr r1, r1, #256 -; CHECK-NEXT: moveq r1, #42 -; CHECK-NEXT: mov r0, r1 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: select_C1_C2_signext: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #165 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: orr r1, r1, #256 +; ARM-NEXT: moveq r1, #42 +; ARM-NEXT: mov r0, r1 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: select_C1_C2_signext: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r0, #42 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movwne r0, #421 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: select_C1_C2_signext: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB23_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #42 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .LBB23_2: +; THUMB-NEXT: movs r0, #255 +; THUMB-NEXT: adds r0, #166 +; THUMB-NEXT: bx lr %sel = select i1 %cond, i32 421, i32 42 ret i32 %sel } @@ -277,26 +624,92 @@ define i32 @select_C1_C2_signext(i1 signext %cond) { ; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select. define i64 @opaque_constant1(i1 %cond, i64 %x) { -; CHECK-LABEL: opaque_constant1: -; CHECK: @ %bb.0: -; CHECK-NEXT: .save {r4, lr} -; CHECK-NEXT: push {r4, lr} -; CHECK-NEXT: mov lr, #1 -; CHECK-NEXT: ands r12, r0, #1 -; CHECK-NEXT: mov r0, #23 -; CHECK-NEXT: orr lr, lr, #65536 -; CHECK-NEXT: mvnne r0, #3 -; CHECK-NEXT: and r4, r0, lr -; CHECK-NEXT: movne r12, #1 -; CHECK-NEXT: subs r0, r4, #1 -; CHECK-NEXT: eor r2, r2, lr -; CHECK-NEXT: eor r3, r3, #1 -; CHECK-NEXT: sbc r1, r12, #0 -; CHECK-NEXT: orrs r2, r2, r3 -; CHECK-NEXT: movne r0, r4 -; CHECK-NEXT: movne r1, r12 -; CHECK-NEXT: pop {r4, lr} -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: opaque_constant1: +; ARM: @ %bb.0: +; ARM-NEXT: .save {r4, lr} +; ARM-NEXT: push {r4, lr} +; ARM-NEXT: mov lr, #1 +; ARM-NEXT: ands r12, r0, #1 +; ARM-NEXT: mov r0, #23 +; ARM-NEXT: orr lr, lr, #65536 +; ARM-NEXT: mvnne r0, #3 +; ARM-NEXT: and r4, r0, lr +; ARM-NEXT: movne r12, #1 +; ARM-NEXT: subs r0, r4, #1 +; ARM-NEXT: eor r2, r2, lr +; ARM-NEXT: eor r3, r3, #1 +; ARM-NEXT: sbc r1, r12, #0 +; ARM-NEXT: orrs r2, r2, r3 +; ARM-NEXT: movne r0, r4 +; ARM-NEXT: movne r1, r12 +; ARM-NEXT: pop {r4, lr} +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: opaque_constant1: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: .save {r7, lr} +; THUMB2-NEXT: push {r7, lr} +; THUMB2-NEXT: ands r12, r0, #1 +; THUMB2-NEXT: mov.w lr, #1 +; THUMB2-NEXT: itt ne +; THUMB2-NEXT: movne.w lr, #65536 +; THUMB2-NEXT: movne.w r12, #1 +; THUMB2-NEXT: subs.w r0, lr, #1 +; THUMB2-NEXT: sbc r1, r12, #0 +; THUMB2-NEXT: eor r3, r3, #1 +; THUMB2-NEXT: eor r2, r2, #65537 +; THUMB2-NEXT: orrs r2, r3 +; THUMB2-NEXT: itt ne +; THUMB2-NEXT: movne r0, lr +; THUMB2-NEXT: movne r1, r12 +; THUMB2-NEXT: pop {r7, pc} +; +; THUMB-LABEL: opaque_constant1: +; THUMB: @ %bb.0: +; THUMB-NEXT: .save {r4, r5, r6, r7, lr} +; THUMB-NEXT: push {r4, r5, r6, r7, lr} +; THUMB-NEXT: movs r7, #1 +; THUMB-NEXT: ands r0, r7 +; THUMB-NEXT: subs r1, r0, #1 +; THUMB-NEXT: push {r0} +; THUMB-NEXT: pop {r4} +; THUMB-NEXT: sbcs r4, r1 +; THUMB-NEXT: cmp r0, #0 +; THUMB-NEXT: bne .LBB24_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r5, #23 +; THUMB-NEXT: b .LBB24_3 +; THUMB-NEXT: .LBB24_2: +; THUMB-NEXT: movs r0, #3 +; THUMB-NEXT: mvns r5, r0 +; THUMB-NEXT: .LBB24_3: +; THUMB-NEXT: ldr r0, .LCPI24_0 +; THUMB-NEXT: ands r5, r0 +; THUMB-NEXT: movs r6, #0 +; THUMB-NEXT: subs r0, r5, #1 +; THUMB-NEXT: push {r4} +; THUMB-NEXT: pop {r1} +; THUMB-NEXT: sbcs r1, r6 +; THUMB-NEXT: eors r3, r7 +; THUMB-NEXT: ldr r6, .LCPI24_0 +; THUMB-NEXT: eors r2, r6 +; THUMB-NEXT: orrs r2, r3 +; THUMB-NEXT: beq .LBB24_5 +; THUMB-NEXT: @ %bb.4: +; THUMB-NEXT: movs r1, r4 +; THUMB-NEXT: .LBB24_5: +; THUMB-NEXT: cmp r2, #0 +; THUMB-NEXT: beq .LBB24_7 +; THUMB-NEXT: @ %bb.6: +; THUMB-NEXT: movs r0, r5 +; THUMB-NEXT: .LBB24_7: +; THUMB-NEXT: pop {r4, r5, r6, r7} +; THUMB-NEXT: pop {r2} +; THUMB-NEXT: bx r2 +; THUMB-NEXT: .p2align 2 +; THUMB-NEXT: @ %bb.8: +; THUMB-NEXT: .LCPI24_0: +; THUMB-NEXT: .long 65537 @ 0x10001 %sel = select i1 %cond, i64 -4, i64 23 %bo = and i64 %sel, 4295032833 ; 0x100010001 %cmp = icmp eq i64 %x, 4295032833 @@ -309,15 +722,43 @@ define i64 @opaque_constant1(i1 %cond, i64 %x) { ; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select. define i64 @opaque_constant2(i1 %cond, i64 %x) { -; CHECK-LABEL: opaque_constant2: -; CHECK: @ %bb.0: -; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: tst r0, #1 -; CHECK-NEXT: orr r1, r1, #65536 -; CHECK-NEXT: moveq r1, #23 -; CHECK-NEXT: bic r0, r1, #22 -; CHECK-NEXT: mov r1, #0 -; CHECK-NEXT: mov pc, lr +; ARM-LABEL: opaque_constant2: +; ARM: @ %bb.0: +; ARM-NEXT: mov r1, #1 +; ARM-NEXT: tst r0, #1 +; ARM-NEXT: orr r1, r1, #65536 +; ARM-NEXT: moveq r1, #23 +; ARM-NEXT: bic r0, r1, #22 +; ARM-NEXT: mov r1, #0 +; ARM-NEXT: mov pc, lr +; +; THUMB2-LABEL: opaque_constant2: +; THUMB2: @ %bb.0: +; THUMB2-NEXT: lsls r0, r0, #31 +; THUMB2-NEXT: mov.w r1, #0 +; THUMB2-NEXT: mov.w r0, #1 +; THUMB2-NEXT: it ne +; THUMB2-NEXT: movne.w r0, #65537 +; THUMB2-NEXT: bx lr +; +; THUMB-LABEL: opaque_constant2: +; THUMB: @ %bb.0: +; THUMB-NEXT: lsls r0, r0, #31 +; THUMB-NEXT: bne .LBB25_2 +; THUMB-NEXT: @ %bb.1: +; THUMB-NEXT: movs r0, #23 +; THUMB-NEXT: b .LBB25_3 +; THUMB-NEXT: .LBB25_2: +; THUMB-NEXT: ldr r0, .LCPI25_0 +; THUMB-NEXT: .LBB25_3: +; THUMB-NEXT: movs r1, #22 +; THUMB-NEXT: bics r0, r1 +; THUMB-NEXT: movs r1, #0 +; THUMB-NEXT: bx lr +; THUMB-NEXT: .p2align 2 +; THUMB-NEXT: @ %bb.4: +; THUMB-NEXT: .LCPI25_0: +; THUMB-NEXT: .long 65537 @ 0x10001 %sel = select i1 %cond, i64 65537, i64 23 %bo = and i64 %sel, 65537 ret i64 %bo