From: Craig Topper Date: Thu, 22 Jun 2023 01:02:53 +0000 (-0700) Subject: [RISCV] Minor refactoring of some code in copyPhysReg. NFC X-Git-Tag: upstream/17.0.6~4266 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=017a24eb1b2dad204bc5a8337719e72ea87c689a;p=platform%2Fupstream%2Fllvm.git [RISCV] Minor refactoring of some code in copyPhysReg. NFC Move some of the vmv.v.i handling into the vmv.v.v if. This reduces the scope of one variable. --- diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index e3f7d97..6195f99 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -417,12 +417,13 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (IsScalableVector) { bool UseVMV_V_V = false; + bool UseVMV_V_I = false; MachineBasicBlock::const_iterator DefMBBI; - unsigned VIOpc; if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { UseVMV_V_V = true; // We only need to handle LMUL = 1/2/4/8 here because we only define // vector register classes for LMUL = 1/2/4/8. + unsigned VIOpc; switch (LMul) { default: llvm_unreachable("Impossible LMUL for vector register copy."); @@ -443,12 +444,11 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, VIOpc = RISCV::PseudoVMV_V_I_M8; break; } - } - bool UseVMV_V_I = false; - if (UseVMV_V_V && (DefMBBI->getOpcode() == VIOpc)) { - UseVMV_V_I = true; - Opc = VIOpc; + if (DefMBBI->getOpcode() == VIOpc) { + UseVMV_V_I = true; + Opc = VIOpc; + } } if (NF == 1) {