From: Kieran Bingham Date: Wed, 16 Dec 2020 15:19:29 +0000 (+0000) Subject: clk: renesas: r8a779a0: Add FCPVD clock support X-Git-Tag: v5.15~1712^2~4^2^2~16 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0177b5090effab70762c774b860df8d298e62ff4;p=platform%2Fkernel%2Flinux-starfive.git clk: renesas: r8a779a0: Add FCPVD clock support Add clocks for the FCP for VSP-D module. Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20201216151931.851547-2-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index aa5389b..8160f41 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -152,6 +152,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), + DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), + DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),