From: Kever Yang Date: Thu, 13 Nov 2014 07:19:21 +0000 (+0800) Subject: clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register X-Git-Tag: v5.15~16605^2~23^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0132234160ae46d8bd4677e37adb0b4366e05b1e;p=platform%2Fkernel%2Flinux-starfive.git clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register According to rk3288 trm, the clk_usbphy480m_gate is located at bit 14 of CRU_CLKGATE5_CON register. Signed-off-by: Kever Yang Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index b4a74c2..f27cdae 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0, RK3288_CLKSEL_CON(13), 11, 2, MFLAGS, - RK3288_CLKGATE_CON(5), 15, GFLAGS), + RK3288_CLKGATE_CON(5), 14, GFLAGS), COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, RK3288_CLKGATE_CON(3), 6, GFLAGS),