From: rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Mon, 27 Aug 2001 22:55:21 +0000 (+0000)
Subject:         * config/m68k/m68k.md (subreghi1ashrdi_const32, bsetmemqi,
X-Git-Tag: upstream/4.9.2~92376
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=00f41fc3f8f5a04011937c29d5f6b86fa83516c1;p=platform%2Fupstream%2Flinaro-gcc.git

    * config/m68k/m68k.md (subreghi1ashrdi_const32, bsetmemqi,
        bsetmemqi+1, strict_low_part peephole): Fix SUBREG_BYTE offset.
        (pushqi1): New.
        (adddi_dilshr32, adddi_dishl32): Only data register can be
        source for mem destination.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@45216 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3d64ee7..27c167f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2001-08-27  Roman Zippel  <zippel@linux-m68k.org>
 
+	* config/m68k/m68k.md (subreghi1ashrdi_const32, bsetmemqi,
+	bsetmemqi+1, strict_low_part peephole): Fix SUBREG_BYTE offset.
+	(pushqi1): New.
+	(adddi_dilshr32, adddi_dishl32): Only data register can be
+	source for mem destination.
+
 	* expmed.c (store_bit_field): Ignore adjustment to bitpos
 	and use bitnum to decide about register move.
 
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 799284b..7bac7c9 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1081,6 +1081,13 @@
   "TARGET_5200"
   "* return output_move_strictqi (operands);")
 
+(define_expand "pushqi1"
+  [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
+   (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
+	(match_operand:QI 0 "general_operand" ""))]
+  "!TARGET_5200"
+  "")
+
 (define_expand "movsf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
@@ -2136,7 +2143,7 @@
 ;;    (plus:DI (match_operand:DI 2 "general_operand" "%0")
 ;;	(lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
 ;;            (const_int 32))))]
-    (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
+    (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
             (const_int 32))
         (match_operand:DI 2 "general_operand" "0,0")))]
   ""
@@ -2155,7 +2162,7 @@
 ;;    (plus:DI (match_operand:DI 2 "general_operand" "%0")
 ;;	(ashift:DI (match_operand:DI 1 "general_operand" "ro")
 ;;            (const_int 32))))]
-    (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
+    (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
             (const_int 32))
         (match_operand:DI 2 "general_operand" "0,0")))]
   ""
@@ -4718,7 +4725,7 @@
 (define_insn "subreghi1ashrdi_const32"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
     (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
-            (const_int 32)) 4))]
+            (const_int 32)) 6))]
   ""
   "*
 {
@@ -5197,7 +5204,7 @@
 (define_insn "bsetmemqi"
   [(set (match_operand:QI 0 "memory_operand" "+m")
 	(ior:QI (subreg:QI (ashift:SI (const_int 1)
-		(match_operand:SI 1 "general_operand" "d")) 0)
+		(match_operand:SI 1 "general_operand" "d")) 3)
 	(match_dup 0)))]
   ""
   "*
@@ -5211,7 +5218,7 @@
   [(set (match_operand:QI 0 "memory_operand" "+m")
 	(ior:QI (subreg:QI (ashift:SI (const_int 1)
 	    (match_operator:SI 2 "extend_operator"
-		[(match_operand 1 "general_operand" "d")])) 0)
+		[(match_operand 1 "general_operand" "d")])) 3)
 	(match_dup 0)))]
   ""
   "*
@@ -7182,7 +7189,7 @@
 (define_peephole
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(const_int 0))
-   (set (strict_low_part (subreg:HI (match_dup 0) 0))
+   (set (strict_low_part (subreg:HI (match_dup 0) 2))
 	(match_operand:HI 1 "general_operand" "rmn"))]
   "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
   "*