From: Jacky Liao Date: Fri, 13 Nov 2020 18:13:27 +0000 (-0500) Subject: drm/amd/display: Add HDR3DLUT and SHAPER memory shutdown support X-Git-Tag: accepted/tizen/unified/20230118.172025~8358^2^2~142 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=00b0ac67811b96d32940fa705fb1405139bb3aab;p=platform%2Fkernel%2Flinux-rpi.git drm/amd/display: Add HDR3DLUT and SHAPER memory shutdown support [Why] The HDR3DLUT and SHAPER memory blocks should be powered down when they're not in use. This will reduce power consumption. [How] 1. Write to HDR3DLUT_MEM_PWR_FORCE to put memory to shutdown when HDR3DLUT is not used. 2. Write to SHAPER_MEM_PWR_FORCE to put memory to shutdown when SHAPER is not used. Signed-off-by: Jacky Liao Reviewed-by: Eric Yang Acked-by: Yongqiang Sun Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c index 052bab3e..6e864b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c @@ -510,6 +510,32 @@ static void dpp3_power_on_blnd_lut( } } +static void dpp3_power_on_hdr3dlut( + struct dpp *dpp_base, + bool power_on) +{ + struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); + + if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { + REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, power_on ? 0 : 3); + if (power_on) + REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); + } +} + +static void dpp3_power_on_shaper( + struct dpp *dpp_base, + bool power_on) +{ + struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); + + if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { + REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, power_on ? 0 : 3); + if (power_on) + REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); + } +} + static void dpp3_configure_blnd_lut( struct dpp *dpp_base, bool is_ram_a) @@ -1095,8 +1121,14 @@ bool dpp3_program_shaper( if (params == NULL) { REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); + if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) + dpp3_power_on_shaper(dpp_base, false); return false; } + + if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) + dpp3_power_on_shaper(dpp_base, true); + current_mode = dpp3_get_shaper_current(dpp_base); if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) @@ -1285,8 +1317,14 @@ bool dpp3_program_3dlut( if (params == NULL) { dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); + if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) + dpp3_power_on_hdr3dlut(dpp_base, false); return false; } + + if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) + dpp3_power_on_hdr3dlut(dpp_base, true); + mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); if (mode == LUT_BYPASS || mode == LUT_RAM_B) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h index 2ae5e1f..6415aaa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h @@ -161,6 +161,8 @@ TF_REG_LIST_DCN20_COMMON(id), \ SRI(CM_BLNDGAM_CONTROL, CM, id), \ SRI(CM_SHAPER_LUT_DATA, CM, id),\ + SRI(CM_MEM_PWR_CTRL2, CM, id), \ + SRI(CM_MEM_PWR_STATUS2, CM, id), \ SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\ SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\ SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\ @@ -344,6 +346,10 @@ #define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\ TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \ + TF_SF(CM0_CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, mask_sh),\ TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \ TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \ TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \ @@ -387,6 +393,8 @@ type CM_BIAS_CR_R;\ type GAMCOR_MEM_PWR_DIS; \ type GAMCOR_MEM_PWR_FORCE; \ + type HDR3DLUT_MEM_PWR_FORCE; \ + type SHAPER_MEM_PWR_FORCE; \ type PRE_DEGAM_MODE;\ type PRE_DEGAM_SELECT;\ type CNVC_ALPHA_PLANE_ENABLE; \ @@ -448,7 +456,9 @@ type CM_BLNDGAM_SELECT_CURRENT; \ type CM_BLNDGAM_SELECT; \ type GAMCOR_MEM_PWR_STATE; \ - type BLNDGAM_MEM_PWR_STATE + type BLNDGAM_MEM_PWR_STATE; \ + type HDR3DLUT_MEM_PWR_STATE; \ + type SHAPER_MEM_PWR_STATE struct dcn3_dpp_shift { DPP_REG_FIELD_LIST_DCN3(uint8_t); @@ -461,6 +471,8 @@ struct dcn3_dpp_mask { #define DPP_DCN3_REG_VARIABLE_LIST_COMMON \ DPP_DCN2_REG_VARIABLE_LIST; \ uint32_t CM_MEM_PWR_STATUS;\ + uint32_t CM_MEM_PWR_STATUS2;\ + uint32_t CM_MEM_PWR_CTRL2;\ uint32_t CM_DEALPHA;\ uint32_t CM_BIAS_CR_R;\ uint32_t CM_BIAS_Y_G_CB_B;\