From: Simon Hausmann <simon.hausmann@digia.com>
Date: Tue, 4 Dec 2012 19:54:54 +0000 (+0100)
Subject: [masm] Implement shl and shr inline
X-Git-Tag: upstream/5.2.1~669^2~659^2~750
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=008e910249fa144408dc0d934e6c274269898b91;p=platform%2Fupstream%2Fqtdeclarative.git

[masm] Implement shl and shr inline

Change-Id: Ibc5475030a68d9270e283aa8ac981661c590a29f
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
---

diff --git a/qv4isel_masm.cpp b/qv4isel_masm.cpp
index 1d26f44..2cf0a74 100644
--- a/qv4isel_masm.cpp
+++ b/qv4isel_masm.cpp
@@ -95,6 +95,36 @@ static JSC::MacroAssembler::Jump masm_mul32(JSC::MacroAssembler* assembler, JSC:
     return assembler->branchMul32(JSC::MacroAssembler::Overflow, imm, reg, reg);
 }
 
+static JSC::MacroAssembler::Jump masm_shl32(JSC::MacroAssembler* assembler, JSC::MacroAssembler::Address addr, JSC::MacroAssembler::RegisterID reg)
+{
+    assembler->load32(addr, InstructionSelection::ScratchRegister);
+    assembler->and32(JSC::MacroAssembler::TrustedImm32(0x1f), InstructionSelection::ScratchRegister);
+    assembler->lshift32(InstructionSelection::ScratchRegister, reg);
+    return JSC::MacroAssembler::Jump();
+}
+
+static JSC::MacroAssembler::Jump masm_shl32(JSC::MacroAssembler* assembler, JSC::MacroAssembler::TrustedImm32 imm, JSC::MacroAssembler::RegisterID reg)
+{
+    imm.m_value &= 0x1f;
+    assembler->lshift32(imm, reg);
+    return JSC::MacroAssembler::Jump();
+}
+
+static JSC::MacroAssembler::Jump masm_shr32(JSC::MacroAssembler* assembler, JSC::MacroAssembler::Address addr, JSC::MacroAssembler::RegisterID reg)
+{
+    assembler->load32(addr, InstructionSelection::ScratchRegister);
+    assembler->and32(JSC::MacroAssembler::TrustedImm32(0x1f), InstructionSelection::ScratchRegister);
+    assembler->rshift32(InstructionSelection::ScratchRegister, reg);
+    return JSC::MacroAssembler::Jump();
+}
+
+static JSC::MacroAssembler::Jump masm_shr32(JSC::MacroAssembler* assembler, JSC::MacroAssembler::TrustedImm32 imm, JSC::MacroAssembler::RegisterID reg)
+{
+    imm.m_value &= 0x1f;
+    assembler->rshift32(imm, reg);
+    return JSC::MacroAssembler::Jump();
+}
+
 #define OP(op) \
     { isel_stringIfy(op), op, 0, 0 }
 
@@ -128,8 +158,8 @@ static const struct BinaryOperationInfo {
     OP(__qmljs_div), // OpDiv
     OP(__qmljs_mod), // OpMod
 
-    OP(__qmljs_shl), // OpLShift
-    OP(__qmljs_shr), // OpRShift
+    INLINE_OP(__qmljs_shl, &masm_shl32, &masm_shl32), // OpLShift
+    INLINE_OP(__qmljs_shr, &masm_shr32, &masm_shr32), // OpRShift
     OP(__qmljs_ushr), // OpURShift
 
     OP(__qmljs_gt), // OpGt
diff --git a/qv4isel_masm_p.h b/qv4isel_masm_p.h
index 4d15fd3..16cd427 100644
--- a/qv4isel_masm_p.h
+++ b/qv4isel_masm_p.h
@@ -65,7 +65,6 @@ public:
     { this->operator()(function); }
     void operator()(IR::Function *function);
 
-protected:
 #if CPU(X86)
 
 #undef VALUE_FITS_IN_REGISTER
@@ -148,6 +147,7 @@ protected:
 #error Argh.
 #endif
 
+protected:
     struct VoidType {};
     static const VoidType Void;