From: Xingyu Wu <xingyu.wu@starfivetech.com>
Date: Fri, 7 Jul 2023 10:50:08 +0000 (+0800)
Subject: riscv: dts: jh7110: Add PLL clock controller node
X-Git-Tag: v2023.10~79^2~6
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=005f9627d02e8ecab3c58c77889060e72f7fa25d;p=platform%2Fkernel%2Fu-boot.git

riscv: dts: jh7110: Add PLL clock controller node

Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 58e332e..7a8141a 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -498,8 +498,14 @@
 		};
 
 		sys_syscon: sys_syscon@13030000 {
-			compatible = "starfive,jh7110-sys-syscon","syscon";
+			compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
 			reg = <0x0 0x13030000 0x0 0x1000>;
+
+			pllclk: clock-controller {
+				compatible = "starfive,jh7110-pll";
+				clocks = <&osc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sysgpio: pinctrl@13040000 {