From: Joseph Lo Date: Mon, 12 Aug 2013 09:40:02 +0000 (+0800) Subject: clk: tegra114: add LP1 suspend/resume support X-Git-Tag: upstream/snapshot3+hdmi~4405^2~13^2~10 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=0017f447cc01fa499f1d10dec09702d381f13fe0;p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git clk: tegra114: add LP1 suspend/resume support When the system suspends to LP1, the CPU clock source is switched to CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock source is controlled by the CCLKG_BURST_POLICY register, and hence this register must be restored during LP1 resume. Cc: Mike Turquette Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f74ed19..806d803 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -293,6 +293,8 @@ #ifdef CONFIG_PM_SLEEP static struct cpu_clk_suspend_context { u32 clk_csite_src; + u32 cclkg_burst; + u32 cclkg_divider; } tegra114_cpu_clk_sctx; #endif @@ -2155,12 +2157,22 @@ static void tegra114_cpu_clock_suspend(void) tegra114_cpu_clk_sctx.clk_csite_src = readl(clk_base + CLK_SOURCE_CSITE); writel(3 << 30, clk_base + CLK_SOURCE_CSITE); + + tegra114_cpu_clk_sctx.cclkg_burst = + readl(clk_base + CCLKG_BURST_POLICY); + tegra114_cpu_clk_sctx.cclkg_divider = + readl(clk_base + CCLKG_BURST_POLICY + 4); } static void tegra114_cpu_clock_resume(void) { writel(tegra114_cpu_clk_sctx.clk_csite_src, clk_base + CLK_SOURCE_CSITE); + + writel(tegra114_cpu_clk_sctx.cclkg_burst, + clk_base + CCLKG_BURST_POLICY); + writel(tegra114_cpu_clk_sctx.cclkg_divider, + clk_base + CCLKG_BURST_POLICY + 4); } #endif