From: Tom Rini <trini@konsulko.com>
Date: Thu, 21 Jul 2016 19:38:13 +0000 (-0400)
Subject: Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"
X-Git-Tag: v2016.09-rc1~72
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;ds=sidebyside;h=95d52733036af7438a5285d729d53844ec48c63e;p=platform%2Fkernel%2Fu-boot.git

Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"

Per Vikas' request, the problem this commit is supposed to be solving is
something he doesn't see and further this introduces additional hardware
requirements.

This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440.

Signed-off-by: Tom Rini <trini@konsulko.com>
---

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
index 0bd4695..38adc4e 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -17,13 +17,11 @@
 enum periph_id {
 	UART1_GPIOA_9_10 = 0,
 	UART2_GPIOD_5_6,
-	UART6_GPIOC_6_7,
 };
 
 enum periph_clock {
 	USART1_CLOCK_CFG = 0,
 	USART2_CLOCK_CFG,
-	USART6_CLOCK_CFG,
 	GPIO_A_CLOCK_CFG,
 	GPIO_B_CLOCK_CFG,
 	GPIO_C_CLOCK_CFG,
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c
index ac47850..78d22d4 100644
--- a/arch/arm/mach-stm32/stm32f7/clock.c
+++ b/arch/arm/mach-stm32/stm32f7/clock.c
@@ -245,9 +245,6 @@ void clock_setup(int peripheral)
 	case USART1_CLOCK_CFG:
 		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
 		break;
-	case USART6_CLOCK_CFG:
-		setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART6EN);
-		break;
 	case GPIO_A_CLOCK_CFG:
 		setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
 		break;
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 47aa058..404fdfa 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -32,7 +32,7 @@ const struct stm32_gpio_ctl gpio_ctl_usart = {
 	.otype = STM32_GPIO_OTYPE_PP,
 	.speed = STM32_GPIO_SPEED_50M,
 	.pupd = STM32_GPIO_PUPD_UP,
-	.af = STM32_GPIO_AF8
+	.af = STM32_GPIO_AF7
 };
 
 const struct stm32_gpio_ctl gpio_ctl_fmc = {
@@ -251,8 +251,8 @@ int dram_init(void)
 }
 
 static const struct stm32_gpio_dsc usart_gpio[] = {
-	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_6},	/* TX */
-	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_7},	/* RX */
+	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
+	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7},	/* RX */
 };
 
 int uart_setup_gpio(void)
@@ -260,7 +260,8 @@ int uart_setup_gpio(void)
 	int i;
 	int rv = 0;
 
-	clock_setup(GPIO_C_CLOCK_CFG);
+	clock_setup(GPIO_A_CLOCK_CFG);
+	clock_setup(GPIO_B_CLOCK_CFG);
 	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
 		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
 		if (rv)
@@ -272,7 +273,7 @@ out:
 }
 
 static const struct stm32x7_serial_platdata serial_platdata = {
-	.base = (struct stm32_usart *)USART6_BASE,
+	.base = (struct stm32_usart *)USART1_BASE,
 	.clock = CONFIG_SYS_CLK_FREQ,
 };
 
@@ -291,7 +292,7 @@ int board_early_init_f(void)
 	int res;
 
 	res = uart_setup_gpio();
-	clock_setup(USART6_CLOCK_CFG);
+	clock_setup(USART1_CLOCK_CFG);
 	if (res)
 		return res;