riscv64: Add RISC-V target

Change-Id: I58a8241b6f91946adb2a9506217928f31cf6d34e
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>

diff --git a/packaging/openblas.spec b/packaging/openblas.spec
index 3bd8eec..9ff2336 100644 (file)
--- a/packaging/openblas.spec
+++ b/packaging/openblas.spec
@@ -160,6 +160,9 @@ export LDFLAGS+="-Wl,-z,noexecstack"
 %ifarch aarch64
 %define openblas_target TARGET=ARMV8
 %endif
+%ifarch riscv64
+%define openblas_target TARGET=RISCV64_GENERIC
+%endif
 
 cd ..
 # Make serial, threaded and OpenMP versions