arch/riscv: fix gcc-14 build 86/317186/2 tizen-v5.10
authorMarek Szyprowski <m.szyprowski@samsung.com>
Thu, 5 Sep 2024 08:52:08 +0000 (10:52 +0200)
committerMarek Szyprowski <m.szyprowski@samsung.com>
Thu, 5 Sep 2024 08:53:46 +0000 (10:53 +0200)
The supervisor virtual memory configuration has been moved from the
mstatus register to the sptbr register. Accordingly, the sptbr register
has been renamed to satp (Supervisor Address Translation and Protection)
to reflect is broadened role.

https://riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf

Suggested-by: Łukasz Stelmach <l.stelmach@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Id0eea3bd4bf20da5a577f9d5b14bf58d591bb58b

arch/riscv/mm/context.c

index 4e022e124ba85130c52557c186be2293df5cc8d9..6add1750d03e6118bae8bd01027d7f7a108a81a1 100644 (file)
@@ -98,7 +98,7 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                        "sfence.vma t0, t0\n\t"
                        ::: "memory", "t0");
 
-       csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE | asid);
+       csr_write(satp, virt_to_pfn(next->pgd) | SATP_MODE | asid);
 #endif
 
        flush_icache_deferred(next);