projects
/
platform
/
upstream
/
openblas.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
71a1083
)
riscv64: Add RISC-V target
44/284644/1
accepted/tizen_8.0_unified
tizen_8.0
accepted/tizen/8.0/unified/20231005.095258
accepted/tizen/unified/20221209.124048
tizen_8.0_m2_release
author
Marek Pikuła
<m.pikula@partner.samsung.com>
Mon, 14 Nov 2022 11:10:23 +0000
(12:10 +0100)
committer
Łukasz Stelmach
<l.stelmach@samsung.com>
Tue, 22 Nov 2022 08:06:56 +0000
(09:06 +0100)
Change-Id: I58a8241b6f91946adb2a9506217928f31cf6d34e
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
packaging/openblas.spec
patch
|
blob
|
history
diff --git
a/packaging/openblas.spec
b/packaging/openblas.spec
index
3bd8eec
..
9ff2336
100644
(file)
--- a/
packaging/openblas.spec
+++ b/
packaging/openblas.spec
@@
-160,6
+160,9
@@
export LDFLAGS+="-Wl,-z,noexecstack"
%ifarch aarch64
%define openblas_target TARGET=ARMV8
%endif
+%ifarch riscv64
+%define openblas_target TARGET=RISCV64_GENERIC
+%endif
cd ..
# Make serial, threaded and OpenMP versions