{
struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
- if (cs->cdw == ctx->start_cs_cmd.num_dw)
- return;
-
ctx->nontimer_queries_suspended = false;
ctx->streamout.suspended = false;
/* Re-emit the draw state. */
ctx->last_primitive_type = -1;
ctx->last_start_instance = -1;
+
+ ctx->initial_gfx_cs_size = ctx->rings.gfx.cs->cdw;
}
void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
unsigned render_cond_mode = 0;
boolean render_cond_cond = FALSE;
+ if (rctx->rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
+ return;
+
rctx->rings.gfx.flushing = true;
/* Disable render condition. */
if (rctx->current_render_cond) {
if (render_cond) {
ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
}
+
+ rctx->initial_gfx_cs_size = rctx->rings.gfx.cs->cdw;
}
static void r600_flush_from_st(struct pipe_context *ctx,
struct u_suballocator *allocator_so_filled_size;
struct u_suballocator *allocator_fetch_shader;
struct util_slab_mempool pool_transfers;
+ unsigned initial_gfx_cs_size;
/* Hardware info. */
enum radeon_family family;