mmc: meson_gx_mmc: control ddr_mode bit

EMMC_CFG register has a cfg_ddr bit(BIT[2]).
It needs to set when mmc is running to ddr mode.
Otherwise, its bit should be cleared.
CFG_DDR[2] - 1: DDR mode, 0: SDR mode

Change-Id: I5b1ddc6492e9c0d90e974fa31b13eacdee6e38e3
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index 1e9f8cf..c2f77c7 100644 (file)
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -38,6 +38,7 @@
 #define   CFG_BUS_WIDTH_1              0
 #define   CFG_BUS_WIDTH_4              1
 #define   CFG_BUS_WIDTH_8              2
+#define   CFG_DDR_MODE                 BIT(2)
 #define   CFG_BL_LEN_MASK              GENMASK(7, 4)
 #define   CFG_BL_LEN_SHIFT             4
 #define   CFG_BL_LEN_512               (9 << 4)

diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 7c60e05..6fcf6c2 100644 (file)
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -90,6 +90,11 @@ static int meson_dm_mmc_set_ios(struct udevice *dev)
        else
                return -EINVAL;
 
+       if (mmc->ddr_mode)
+               meson_mmc_cfg |= CFG_DDR_MODE;
+       else
+               meson_mmc_cfg &= ~CFG_DDR_MODE;
+
        /* 512 bytes block length */
        meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
        meson_mmc_cfg |= CFG_BL_LEN_512;