riscv: dts: starfive: Add full support for JH7110 and VisionFive 2 board

Merge all StarFive dts patches together.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
 Conflicts:
	arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
	arch/riscv/boot/dts/starfive/jh7110.dtsi

[Backported from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream]
Change-Id: I0b498d1c7694877a210026717bd1c4e8fffac22a
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 752bb0b..63eecf3 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -219,6 +219,20 @@
        status = "okay";
 };
 
+&pcie0 {
+       pinctrl-names = "default";
+       reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+       phys = <&pciephy0>;
+       status = "okay";
+};
+
+&pcie1 {
+       pinctrl-names = "default";
+       reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+       phys = <&pciephy1>;
+       status = "okay";
+};
+
 &ptc {
        pinctrl-names = "default";
        pinctrl-0 = <&pwm_pins>;
@@ -282,6 +296,50 @@
                };
        };
 
+       pcie0_wake_default: pcie0_wake_default {
+               wake-pins {
+                       pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+                       bias-disable;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
+       pcie0_clkreq_default: pcie0_clkreq_default {
+               clkreq-pins {
+                       bias-disable;
+                       pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
+       pcie1_wake_default: pcie1_wake_default {
+               wake-pins {
+                       bias-disable;
+                       pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
+       pcie1_clkreq_default: pcie1_clkreq_default {
+               clkreq-pins {
+                       bias-disable;
+                       pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
        pwm_pins: pwm-0 {
                pwm-pins {
                        pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 95abd5f..08b6bcd 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -922,5 +922,93 @@
                        #reset-cells = <1>;
                        power-domains = <&pwrc JH7110_PD_VOUT>;
                };
+
+               pcie0: pcie@2B000000 {
+                       compatible = "starfive,jh7110-pcie";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       reg = <0x0 0x2B000000 0x0 0x1000000
+                              0x9 0x40000000 0x0 0x10000000>;
+                       reg-names = "reg", "config";
+                       device_type = "pci";
+                       starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
+                       interrupts = <56>;
+                       interrupt-parent = <&plic>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+                       msi-parent = <&pcie0>;
+                       msi-controller;
+                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+                       clock-names = "noc", "tl", "axi_mst0", "apb";
+                       resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
+                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
+                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
+                                <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+                                <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+                                <&stgcrg JH7110_STGRST_PCIE0_APB>;
+                       reset-names = "mst0", "slv0", "slv", "brg",
+                                     "core", "apb";
+                       status = "disabled";
+
+                       pcie_intc0: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               pcie1: pcie@2C000000 {
+                       compatible = "starfive,jh7110-pcie";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       reg = <0x0 0x2C000000 0x0 0x1000000
+                              0x9 0xc0000000 0x0 0x10000000>;
+                       reg-names = "reg", "config";
+                       device_type = "pci";
+                       starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
+                       interrupts = <57>;
+                       interrupt-parent = <&plic>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
+                       msi-parent = <&pcie1>;
+                       msi-controller;
+                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+                       clock-names = "noc", "tl", "axi_mst0", "apb";
+                       resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
+                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
+                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
+                                <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+                                <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+                                <&stgcrg JH7110_STGRST_PCIE1_APB>;
+                       reset-names = "mst0", "slv0", "slv", "brg",
+                                     "core", "apb";
+                       status = "disabled";
+
+                       pcie_intc1: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
        };
 };