riscv: jh7110: Fix build error during backporting

Fix build error during backporting baed on latest version.
This patch is for only v2022.10.

Change-Id: I2dd22cdf1672d3c397c16f546d87496a15b7f61d
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 2ad3f20..482f1f7 100644 (file)
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -21,7 +21,7 @@ int dram_init_banksize(void)
        return fdtdec_setup_memory_banksize();
 }
 
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+ulong board_get_usable_ram_top(ulong total_size)
 {
        /*
         * Ensure that we run from first 4GB so that all

diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig
index 2186a93..f9a373d 100644 (file)
--- a/board/starfive/visionfive2/Kconfig
+++ b/board/starfive/visionfive2/Kconfig
@@ -12,7 +12,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
        default "starfive-visionfive2"
 
-config TEXT_BASE
+config SYS_TEXT_BASE
        default 0x40200000 if SPL
        default 0x40000000 if !RISCV_SMODE
        default 0x40200000 if RISCV_SMODE