#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
-#ifdef ALIGN_EIGHT
-#define TBM_SURFACE_ALIGNMENT_PLANE (8)
-#define TBM_SURFACE_ALIGNMENT_PITCH_RGB (8)
-#else
#define TBM_SURFACE_ALIGNMENT_PLANE (16)
#define TBM_SURFACE_ALIGNMENT_PITCH_RGB (16)
-#endif
#define TBM_SURFACE_ALIGNMENT_PLANE_NV12 (4096)
#define TBM_SURFACE_ALIGNMENT_PITCH_YUV (32)
#define TBM_SURFACE_ALIGNMENT_HEIGHT_YUV (16)
-struct dma_buf_info {
- unsigned long size;
- unsigned int fence_supported;
- unsigned int padding;
-};
-
-#define DMA_BUF_ACCESS_READ 0x1
-#define DMA_BUF_ACCESS_WRITE 0x2
-#define DMA_BUF_ACCESS_DMA 0x4
-#define DMA_BUF_ACCESS_MAX 0x8
-
-#define DMA_FENCE_LIST_MAX 5
-
-struct dma_buf_fence {
- unsigned long ctx;
- unsigned int type;
-};
-
-#define DMABUF_IOCTL_BASE 'F'
-#define DMABUF_IOWR(nr, type) _IOWR(DMABUF_IOCTL_BASE, nr, type)
-
-#define DMABUF_IOCTL_GET_INFO DMABUF_IOWR(0x00, struct dma_buf_info)
-#define DMABUF_IOCTL_GET_FENCE DMABUF_IOWR(0x01, struct dma_buf_fence)
-#define DMABUF_IOCTL_PUT_FENCE DMABUF_IOWR(0x02, struct dma_buf_fence)
-
-/* tgl key values */
-#define GLOBAL_KEY ((unsigned int)(-1))
-/* TBM_CACHE */
-#define TBM_VC4_CACHE_INV 0x01 /**< cache invalidate */
-#define TBM_VC4_CACHE_CLN 0x02 /**< cache clean */
-#define TBM_VC4_CACHE_ALL 0x10 /**< cache all */
-#define TBM_VC4_CACHE_FLUSH (TBM_VC4_CACHE_INV|TBM_VC4_CACHE_CLN) /**< cache flush */
-#define TBM_VC4_CACHE_FLUSH_ALL (TBM_VC4_CACHE_FLUSH|TBM_VC4_CACHE_ALL) /**< cache flush all */
-
-enum {
- DEVICE_NONE = 0,
- DEVICE_CA, /* cache aware device */
- DEVICE_CO /* cache oblivious device */
-};
-
-typedef union _tbm_bo_cache_state tbm_bo_cache_state;
-
-union _tbm_bo_cache_state {
- unsigned int val;
- struct {
- unsigned int cntFlush:16; /*Flush all index for sync */
- unsigned int isCached:1;
- unsigned int isDirtied:2;
- } data;
-};
-
typedef struct _tbm_vc4_bufmgr tbm_vc4_bufmgr;
typedef struct _tbm_vc4_surface tbm_vc4_surface;
typedef struct _tbm_vc4_bo tbm_vc4_bo;
unsigned int flags_tbm; /*not used now*//*currently no values for the flags,but it may be used in future extension*/
pthread_mutex_t mutex;
- struct dma_buf_fence dma_fence[DMA_FENCE_LIST_MAX];
int device;
int opt;
- tbm_bo_cache_state cache_state;
unsigned int map_cnt;
int last_map_device;
void *hashBos;
struct list_head surface_data_list;
-
- int use_dma_fence;
-
- int tgl_fd;
};
static char *STR_DEVICE[] = {
static hal_tbm_bo *tbm_vc4_bufmgr_import_fd(hal_tbm_bufmgr *bufmgr, hal_tbm_fd key, hal_tbm_error *error);
static hal_tbm_fd tbm_vc4_bo_export_fd(hal_tbm_bo *bo, hal_tbm_error *error);
-#undef ENABLE_CACHECRTL
-#ifdef ENABLE_CACHECRTL
-#ifdef TGL_GET_VERSION
-static inline int
-_tgl_get_version(int fd)
-{
- struct tgl_ver_data data;
- int err;
- char buf[STRERR_BUFSIZE];
-
- err = ioctl(fd, TGL_IOCTL_GET_VERSION, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) %s:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE));
- return 0;
- }
-
- TBM_BACKEND_DBG("tgl version is (%u, %u).\n", data.major, data.minor);
-
- return 1;
-}
-#endif
-
-static inline int
-_tgl_init(int fd, unsigned int key)
-{
- struct tgl_reg_data data;
- int err;
- char buf[STRERR_BUFSIZE];
-
- data.key = key;
- data.timeout_ms = 1000;
-
- err = ioctl(fd, TGL_IOCTL_REGISTER, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) key:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE), key);
- return 0;
- }
-
- return 1;
-}
-
-static inline int
-_tgl_destroy(int fd, unsigned int key)
-{
- struct tgl_reg_data data;
- int err;
- char buf[STRERR_BUFSIZE];
-
- data.key = key;
- err = ioctl(fd, TGL_IOCTL_UNREGISTER, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) key:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE), key);
- return 0;
- }
-
- return 1;
-}
-
-static inline int
-_tgl_lock(int fd, unsigned int key, int opt)
-{
- struct tgl_lock_data data;
- enum tgl_type_data tgl_type;
- int err;
- char buf[STRERR_BUFSIZE];
-
- switch (opt) {
- case TBM_OPTION_READ:
- tgl_type = TGL_TYPE_READ;
- break;
- case TBM_OPTION_WRITE:
- tgl_type = TGL_TYPE_WRITE;
- break;
- default:
- tgl_type = TGL_TYPE_NONE;
- break;
- }
-
- data.key = key;
- data.type = tgl_type;
-
- err = ioctl(fd, TGL_IOCTL_LOCK, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) key:%d opt:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE), key, opt);
- return 0;
- }
-
- return 1;
-}
-
-static inline int
-_tgl_unlock(int fd, unsigned int key)
-{
- struct tgl_lock_data data;
- int err;
- char buf[STRERR_BUFSIZE];
-
- data.key = key;
- data.type = TGL_TYPE_NONE;
-
- err = ioctl(fd, TGL_IOCTL_UNLOCK, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) key:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE), key);
- return 0;
- }
-
- return 1;
-}
-
-static inline int
-_tgl_set_data(int fd, unsigned int key, unsigned int val)
-{
- struct tgl_usr_data data;
- int err;
- char buf[STRERR_BUFSIZE];
-
- data.key = key;
- data.data1 = val;
-
- err = ioctl(fd, TGL_IOCTL_SET_DATA, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) key:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE), key);
- return 0;
- }
-
- return 1;
-}
-
-static inline unsigned int
-_tgl_get_data(int fd, unsigned int key)
-{
- struct tgl_usr_data data = { 0, };
- int err;
- char buf[STRERR_BUFSIZE];
-
- data.key = key;
-
- err = ioctl(fd, TGL_IOCTL_GET_DATA, &data);
- if (err) {
- TBM_BACKEND_ERR("error(%s) key:%d\n",
- strerror_r(errno, buf, STRERR_BUFSIZE), key);
- return 0;
- }
-
- return data.data1;
-}
-
-static int
-_vc4_cache_flush(tbm_vc4_bufmgr *bufmgr_data, tbm_vc4_bo *bo_data, int flags)
-{
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bufmgr_data != NULL, 0);
-
- /* cache flush is managed by kernel side when using dma-fence. */
- if (bufmgr_data->use_dma_fence)
- return 1;
-
- struct drm_vc4_gem_cache_op cache_op = {0, };
- int ret;
-
- /* if bo_data is null, do cache_flush_all */
- if (bo_data) {
- cache_op.flags = 0;
- cache_op.usr_addr = (uint64_t)((uint32_t)bo_data->pBase);
- cache_op.size = bo_data->size;
- } else {
- flags = TBM_VC4_CACHE_FLUSH_ALL;
- cache_op.flags = 0;
- cache_op.usr_addr = 0;
- cache_op.size = 0;
- }
-
- if (flags & TBM_VC4_CACHE_INV) {
- if (flags & TBM_VC4_CACHE_ALL)
- cache_op.flags |= VC4_DRM_CACHE_INV_ALL;
- else
- cache_op.flags |= VC4_DRM_CACHE_INV_RANGE;
- }
-
- if (flags & TBM_VC4_CACHE_CLN) {
- if (flags & TBM_VC4_CACHE_ALL)
- cache_op.flags |= VC4_DRM_CACHE_CLN_ALL;
- else
- cache_op.flags |= VC4_DRM_CACHE_CLN_RANGE;
- }
-
- if (flags & TBM_VC4_CACHE_ALL)
- cache_op.flags |= VC4_DRM_ALL_CACHES_CORES;
-
- ret = drmCommandWriteRead(bufmgr_data->fd, DRM_VC4_GEM_CACHE_OP, &cache_op,
- sizeof(cache_op));
- if (ret) {
- TBM_BACKEND_ERR("fail to flush the cache.\n");
- return 0;
- }
-
- return 1;
-}
-#endif
-
-static int
-_bo_init_cache_state(tbm_vc4_bufmgr *bufmgr_data, tbm_vc4_bo *bo_data, int import)
-{
-#ifdef ENABLE_CACHECRTL
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bufmgr_data != NULL, 0);
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bo_data != NULL, 0);
-
- if (bufmgr_data->use_dma_fence)
- return 1;
-
- _tgl_init(bufmgr_data->tgl_fd, bo_data->name);
-
- tbm_bo_cache_state cache_state;
-
- if (import == 0) {
- cache_state.data.isDirtied = DEVICE_NONE;
- cache_state.data.isCached = 0;
- cache_state.data.cntFlush = 0;
-
- _tgl_set_data(bufmgr_data->tgl_fd, bo_data->name, cache_state.val);
- }
-#endif
-
- return 1;
-}
-
-static int
-_bo_set_cache_state(tbm_vc4_bufmgr *bufmgr_data, tbm_vc4_bo *bo_data, int device, int opt)
-{
-#ifdef ENABLE_CACHECRTL
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bufmgr_data != NULL, 0);
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bo_data != NULL, 0);
-
- if (bufmgr_data->use_dma_fence)
- return 1;
-
- char need_flush = 0;
- unsigned short cntFlush = 0;
-
- /* get cache state of a bo_data */
- bo_data->cache_state.val = _tgl_get_data(bufmgr_data->tgl_fd,
- bo_data->name);
-
- /* get global cache flush count */
- cntFlush = (unsigned short)_tgl_get_data(bufmgr_data->tgl_fd, GLOBAL_KEY);
-
- if (device == HAL_TBM_DEVICE_CPU) {
- if (bo_data->cache_state.data.isDirtied == DEVICE_CO &&
- bo_data->cache_state.data.isCached)
- need_flush = TBM_VC4_CACHE_INV;
-
- bo_data->cache_state.data.isCached = 1;
- if (opt & TBM_OPTION_WRITE)
- bo_data->cache_state.data.isDirtied = DEVICE_CA;
- else {
- if (bo_data->cache_state.data.isDirtied != DEVICE_CA)
- bo_data->cache_state.data.isDirtied = DEVICE_NONE;
- }
- } else {
- if (bo_data->cache_state.data.isDirtied == DEVICE_CA &&
- bo_data->cache_state.data.isCached &&
- bo_data->cache_state.data.cntFlush == cntFlush)
- need_flush = TBM_VC4_CACHE_CLN | TBM_VC4_CACHE_ALL;
-
- if (opt & TBM_OPTION_WRITE)
- bo_data->cache_state.data.isDirtied = DEVICE_CO;
- else {
- if (bo_data->cache_state.data.isDirtied != DEVICE_CO)
- bo_data->cache_state.data.isDirtied = DEVICE_NONE;
- }
- }
-
- if (need_flush) {
- if (need_flush & TBM_VC4_CACHE_ALL)
- _tgl_set_data(bufmgr_data->tgl_fd, GLOBAL_KEY, (unsigned int)(++cntFlush));
-
- /* call cache flush */
- _vc4_cache_flush(bufmgr_data, bo_data, need_flush);
-
- TBM_BACKEND_DBG(" \tcache(%d,%d)....flush:0x%x, cntFlush(%d)\n",
- bo_data->cache_state.data.isCached,
- bo_data->cache_state.data.isDirtied,
- need_flush,
- cntFlush);
- }
-#endif
-
- return 1;
-}
-
-static int
-_bo_save_cache_state(tbm_vc4_bufmgr *bufmgr_data, tbm_vc4_bo *bo_data)
-{
-#ifdef ENABLE_CACHECRTL
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bufmgr_data != NULL, 0);
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bo_data != NULL, 0);
-
- if (bufmgr_data->use_dma_fence)
- return 1;
-
- unsigned short cntFlush = 0;
-
- /* get global cache flush count */
- cntFlush = (unsigned short)_tgl_get_data(bufmgr_data->tgl_fd, GLOBAL_KEY);
-
- /* save global cache flush count */
- bo_data->cache_state.data.cntFlush = cntFlush;
- _tgl_set_data(bufmgr_data->tgl_fd, bo_data->name,
- bo_data->cache_state.val);
-#endif
-
- return 1;
-}
-
-static void
-_bo_destroy_cache_state(tbm_vc4_bufmgr *bufmgr_data, tbm_vc4_bo *bo_data)
-{
-#ifdef ENABLE_CACHECRTL
- TBM_BACKEND_RETURN_IF_FAIL(bufmgr_data != NULL);
- TBM_BACKEND_RETURN_IF_FAIL(bo_data != NULL);
-
- if (bufmgr_data->use_dma_fence)
- return ;
-
- _tgl_destroy(bufmgr_data->tgl_fd, bo_data->name);
-#endif
-}
-
-static int
-_bufmgr_init_cache_state(tbm_vc4_bufmgr *bufmgr_data)
-{
-#ifdef ENABLE_CACHECRTL
- TBM_BACKEND_RETURN_VAL_IF_FAIL(bufmgr_data != NULL, 0);
-
- if (bufmgr_data->use_dma_fence)
- return 1;
-
- /* open tgl fd for saving cache flush data */
- bufmgr_data->tgl_fd = open(tgl_devfile, O_RDWR);
-
- if (bufmgr_data->tgl_fd < 0) {
- bufmgr_data->tgl_fd = open(tgl_devfile1, O_RDWR);
- if (bufmgr_data->tgl_fd < 0) {
- TBM_BACKEND_ERR("fail to open global_lock:%s\n",
- tgl_devfile1);
- return 0;
- }
- }
-
-#ifdef TGL_GET_VERSION
- if (!_tgl_get_version(bufmgr_data->tgl_fd)) {
- TBM_BACKEND_ERR("fail to get tgl_version. tgl init failed.\n");
- close(bufmgr_data->tgl_fd);
- return 0;
- }
-#endif
-
- if (!_tgl_init(bufmgr_data->tgl_fd, GLOBAL_KEY)) {
- TBM_BACKEND_ERR("fail to initialize the tgl\n");
- close(bufmgr_data->tgl_fd);
- return 0;
- }
-#endif
-
- return 1;
-}
-
-static void
-_bufmgr_deinit_cache_state(tbm_vc4_bufmgr *bufmgr_data)
-{
-#ifdef ENABLE_CACHECRTL
- TBM_BACKEND_RETURN_IF_FAIL(bufmgr_data != NULL);
-
- if (bufmgr_data->use_dma_fence)
- return;
-
- if (bufmgr_data->tgl_fd >= 0)
- close(bufmgr_data->tgl_fd);
-#endif
-}
-
static int
_tbm_vc4_open_drm()
{
bo_data->flags_tbm = flags;
bo_data->name = _get_name(bo_data->fd, bo_data->gem);
- if (!_bo_init_cache_state(bufmgr_data, bo_data, 0)) {
- TBM_BACKEND_ERR("fail init cache state(%d)\n", bo_data->name);
- free(bo_data);
- if (error)
- *error = HAL_TBM_ERROR_INVALID_OPERATION;
- return NULL;
- }
-
pthread_mutex_init(&bo_data->mutex, NULL);
- if (bufmgr_data->use_dma_fence && !bo_data->dmabuf) {
+ if (!bo_data->dmabuf) {
struct drm_prime_handle arg = {0, };
arg.handle = bo_data->gem;
bo_data->name = name;
bo_data->flags_tbm = 0;
- if (!_bo_init_cache_state(bufmgr_data, bo_data, 1)) {
- TBM_BACKEND_ERR("fail init cache state(%d)\n", bo_data->name);
- free(bo_data);
- if (error)
- *error = HAL_TBM_ERROR_INVALID_OPERATION;
- return NULL;
- }
-
/* add bo_data to hash */
if (drmHashInsert(bufmgr_data->hashBos, bo_data->name, (void *)bo_data) < 0)
TBM_BACKEND_ERR("bo_data:%p Cannot insert bo_data to Hash(%d) from gem:%d, fd:%d\n",
bo_data->name = key;
bo_data->flags_tbm = 0;
- if (!_bo_init_cache_state(bufmgr_data, bo_data, 1)) {
- TBM_BACKEND_ERR("fail init cache state(%d)\n", bo_data->name);
- free(bo_data);
- if (error)
- *error = HAL_TBM_ERROR_INVALID_OPERATION;
- return NULL;
- }
-
if (!bo_data->dmabuf) {
struct drm_prime_handle arg = {0, };
if (temp != bo_data)
TBM_BACKEND_ERR("hashBos probably has several BOs with same name!!!\n");
- _bo_destroy_cache_state(bufmgr_data, bo_data);
-
/* Free gem handle */
struct drm_gem_close arg = {0, };
return (hal_tbm_bo_handle) NULL;
}
- if (bo_data->map_cnt == 0)
- _bo_set_cache_state(bufmgr_data, bo_data, device, opt);
-
bo_data->last_map_device = device;
bo_data->map_cnt++;
bo_data->map_cnt--;
- if (bo_data->map_cnt == 0)
- _bo_save_cache_state(bufmgr_data, bo_data);
-
-#ifdef ENABLE_CACHECRTL
- if (bo_data->last_map_device == HAL_TBM_DEVICE_CPU)
- _vc4_cache_flush(bufmgr_data, bo_data, TBM_VC4_CACHE_FLUSH_ALL);
-#endif
-
bo_data->last_map_device = -1;
TBM_BACKEND_DBG(" bo_data:%p, gem:%d(%d), fd:%d\n",
tbm_vc4_bo_lock(hal_tbm_bo *bo, hal_tbm_bo_device_type device,
hal_tbm_bo_access_option opt)
{
-#ifndef ALWAYS_BACKEND_CTRL
- tbm_vc4_bo *bo_data = (tbm_vc4_bo *)bo;
- tbm_vc4_bufmgr *bufmgr_data;
- struct dma_buf_fence fence;
- struct flock filelock;
- int ret = 0;
- char buf[STRERR_BUFSIZE];
-
- if (!bo_data)
- return HAL_TBM_ERROR_INVALID_PARAMETER;
-
- bufmgr_data = bo_data->bufmgr_data;
- if (!bufmgr_data)
- return HAL_TBM_ERROR_INVALID_PARAMETER;
-
- if (device != HAL_TBM_DEVICE_3D && device != HAL_TBM_DEVICE_CPU) {
- TBM_BACKEND_DBG("Not support device type,\n");
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
-
- memset(&fence, 0, sizeof(struct dma_buf_fence));
-
- /* Check if the given type is valid or not. */
- if (opt & TBM_OPTION_WRITE) {
- if (device == HAL_TBM_DEVICE_3D)
- fence.type = DMA_BUF_ACCESS_WRITE | DMA_BUF_ACCESS_DMA;
- } else if (opt & TBM_OPTION_READ) {
- if (device == HAL_TBM_DEVICE_3D)
- fence.type = DMA_BUF_ACCESS_READ | DMA_BUF_ACCESS_DMA;
- } else {
- TBM_BACKEND_ERR("Invalid argument\n");
- return HAL_TBM_ERROR_INVALID_PARAMETER;
- }
-
- /* Check if the tbm manager supports dma fence or not. */
- if (!bufmgr_data->use_dma_fence) {
- TBM_BACKEND_ERR("Not support DMA FENCE(%s)\n", strerror_r(errno, buf, STRERR_BUFSIZE));
- return HAL_TBM_ERROR_INVALID_OPERATION;
-
- }
-
- if (device == HAL_TBM_DEVICE_3D) {
- ret = ioctl(bo_data->dmabuf, DMABUF_IOCTL_GET_FENCE, &fence);
- if (ret < 0) {
- TBM_BACKEND_ERR("Cannot set GET FENCE(%s)\n", strerror_r(errno, buf, STRERR_BUFSIZE));
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
- } else {
- if (opt & TBM_OPTION_WRITE)
- filelock.l_type = F_WRLCK;
- else
- filelock.l_type = F_RDLCK;
-
- filelock.l_whence = SEEK_CUR;
- filelock.l_start = 0;
- filelock.l_len = 0;
-
- if (-1 == fcntl(bo_data->dmabuf, F_SETLKW, &filelock))
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
-
- pthread_mutex_lock(&bo_data->mutex);
-
- if (device == HAL_TBM_DEVICE_3D) {
- int i;
-
- for (i = 0; i < DMA_FENCE_LIST_MAX; i++) {
- if (bo_data->dma_fence[i].ctx == 0) {
- bo_data->dma_fence[i].type = fence.type;
- bo_data->dma_fence[i].ctx = fence.ctx;
- break;
- }
- }
-
- if (i == DMA_FENCE_LIST_MAX) {
- /*TODO: if dma_fence list is full, it needs realloc. I will fix this. by minseok3.kim*/
- TBM_BACKEND_ERR("fence list is full\n");
- }
- }
-
- pthread_mutex_unlock(&bo_data->mutex);
-
- TBM_BACKEND_DBG("DMABUF_IOCTL_GET_FENCE! bo_data:%p, gem:%d(%d), fd:%ds\n",
- bo_data,
- bo_data->gem, bo_data->name,
- bo_data->dmabuf);
-#endif /* ALWAYS_BACKEND_CTRL */
-
return HAL_TBM_ERROR_NONE;
}
static hal_tbm_error
tbm_vc4_bo_unlock(hal_tbm_bo *bo)
{
-#ifndef ALWAYS_BACKEND_CTRL
- tbm_vc4_bo *bo_data = (tbm_vc4_bo *)bo;
- struct dma_buf_fence fence;
- struct flock filelock;
- unsigned int dma_type = 0;
- int ret = 0;
- char buf[STRERR_BUFSIZE];
-
- bufmgr_data = bo_data->bufmgr_data;
- if (!bufmgr_data)
- return HAL_TBM_ERROR_INVALID_PARAMETER;
-
- if (bo_data->dma_fence[0].type & DMA_BUF_ACCESS_DMA)
- dma_type = 1;
-
- if (!bo_data->dma_fence[0].ctx && dma_type) {
- TBM_BACKEND_DBG("FENCE not support or ignored,\n");
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
-
- if (!bo_data->dma_fence[0].ctx && dma_type) {
- TBM_BACKEND_DBG("device type is not 3D/CPU,\n");
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
-
- pthread_mutex_lock(&bo_data->mutex);
-
- if (dma_type) {
- fence.type = bo_data->dma_fence[0].type;
- fence.ctx = bo_data->dma_fence[0].ctx;
- int i;
-
- for (i = 1; i < DMA_FENCE_LIST_MAX; i++) {
- bo_data->dma_fence[i - 1].type = bo_data->dma_fence[i].type;
- bo_data->dma_fence[i - 1].ctx = bo_data->dma_fence[i].ctx;
- }
- bo_data->dma_fence[DMA_FENCE_LIST_MAX - 1].type = 0;
- bo_data->dma_fence[DMA_FENCE_LIST_MAX - 1].ctx = 0;
- }
-
- pthread_mutex_unlock(&bo_data->mutex);
-
- if (dma_type) {
- ret = ioctl(bo_data->dmabuf, DMABUF_IOCTL_PUT_FENCE, &fence);
- if (ret < 0) {
- TBM_BACKEND_ERR("Can not set PUT FENCE(%s)\n", strerror_r(errno, buf, STRERR_BUFSIZE));
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
- } else {
- filelock.l_type = F_UNLCK;
- filelock.l_whence = SEEK_CUR;
- filelock.l_start = 0;
- filelock.l_len = 0;
-
- if (-1 == fcntl(bo_data->dmabuf, F_SETLKW, &filelock))
- return HAL_TBM_ERROR_INVALID_OPERATION;
- }
-
- TBM_BACKEND_DBG("DMABUF_IOCTL_PUT_FENCE! bo_data:%p, gem:%d(%d), fd:%ds\n",
- bo_data,
- bo_data->gem, bo_data->name,
- bo_data->dmabuf);
-#endif /* ALWAYS_BACKEND_CTRL */
-
return HAL_TBM_ERROR_NONE;
}
drmHashDestroy(bufmgr_data->hashBos);
}
- _bufmgr_deinit_cache_state(bufmgr_data);
-
close(bufmgr_data->fd);
free(backend_data->bufmgr);
hal_tbm_bo_funcs *bo_funcs = NULL;
tbm_vc4_bufmgr *bufmgr_data = NULL;
int drm_fd = -1;
- int fp;
/* allocate a hal_tbm_backend_data */
backend_data = calloc(1, sizeof(struct _hal_tbm_backend_data));
TBM_BACKEND_INFO("A backend requests an authenticated drm_fd.\n");
}
- //Check if the tbm manager supports dma fence or not.
- fp = open("/sys/module/dmabuf_sync/parameters/enabled", O_RDONLY);
- if (fp != -1) {
- char buf[1];
- int length = read(fp, buf, 1);
-
- if (length == 1 && buf[0] == '1')
- bufmgr_data->use_dma_fence = 1;
-
- close(fp);
- }
-
- if (!_bufmgr_init_cache_state(bufmgr_data)) {
- TBM_BACKEND_ERR("fail to init bufmgr cache state\n");
- goto fail_init_cache_state;
- }
-
/*Create Hash Table*/
bufmgr_data->hashBos = drmHashCreate();
fail_alloc_surface_funcs:
free(bufmgr_funcs);
fail_alloc_bufmgr_funcs:
- _bufmgr_deinit_cache_state(bufmgr_data);
if (bufmgr_data->hashBos)
drmHashDestroy(bufmgr_data->hashBos);
-fail_init_cache_state:
close(bufmgr_data->fd);
fail_open_drm:
free(bufmgr_data);
projects / platform / adaptation / broadcom / libtbm-vc4.git / commitdiff