#define CONSTANT_BUFFER_0_ADDR_SPACE 8
#define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + R600_UCP_CONST_BUFFER)
+#define CONSTANT_TXQ_BUFFER (CONSTANT_BUFFER_0_ADDR_SPACE + R600_TXQ_CONST_BUFFER)
static LLVMValueRef llvm_load_const_buffer(
struct lp_build_tgsi_context * bld_base,
emit_data->output[0] = build_intrinsic(gallivm->builder,
action->intr_name,
emit_data->dst_type, args, c, LLVMReadNoneAttribute);
+
+ if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
+ ((emit_data->inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
+ emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
+ if (emit_data->inst->Dst[0].Register.WriteMask & 4) {
+ LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, 0);
+ LLVMValueRef ZLayer = LLVMBuildExtractElement(gallivm->builder,
+ llvm_load_const_buffer(bld_base, offset, CONSTANT_TXQ_BUFFER),
+ lp_build_const_int32(gallivm, 0), "");
+
+ emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder, emit_data->output[0], ZLayer, lp_build_const_int32(gallivm, 2), "");
+ struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
+ ctx->has_txq_cube_array_z_comp = true;
+ }
}
static void emit_cndlt(
radeon_llvm_ctx.clip_vertex = ctx.cv_output;
radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
+ ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, dump)) {
radeon_llvm_dispose(&radeon_llvm_ctx);