board: samsung: espress3250: fix the wrong comment style

Fix the wrong comment style.

Change-Id: Ibb3d20d09921f19b9772226ca26f5a4564c76b90
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/board/samsung/espresso3250/smdk3250_val.h b/board/samsung/espresso3250/smdk3250_val.h
index 6870f8fa96fc67ed04f62e8635d084f23da40e0c..81b90f66e18fa3a34070d82da35972af39e77d40 100644 (file)
--- a/board/samsung/espresso3250/smdk3250_val.h
+++ b/board/samsung/espresso3250/smdk3250_val.h
@@ -332,7 +332,7 @@
 #define VPLL_CON0_VAL  set_pll(VPLL_MDIV,VPLL_PDIV,VPLL_SDIV)
 
 /********************************************************/
-/* CPU Clock
+/* CPU Clock */
 /********************************************************/
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL                                                   0
@@ -373,7 +373,7 @@
 #define CLK_DIV_CPU1_VAL       ((HPM_RATIO << 4) | (COPY_RATIO))
 
 /********************************************************/
-/* DMC Clock
+/* DMC Clock */
 /********************************************************/
 /* CLK_SRC_DMC */
 #define MUX_MPLL_USR_SEL_FINPLL                                                0
@@ -427,13 +427,13 @@
                                | (DMC_RATIO_SLEEP << 27)   \
                                | (DPHY_RATIO << 23)    \
                                | (DMC_RATIO_PRE << 19) \
-                               | (3 << 15)     \                               
+                               | (3 << 15)     \
                                | (DMCD_RATIO << 11)    \
                                | (AUDIOCODEC_RATIO))
 
 
 /********************************************************/
-/* ACP Clock
+/* ACP Clock */
 /********************************************************/
 /* CLK_SRC_ACP */
 #define MUX_G2D_ACP_SEL                                                                0x0
@@ -464,7 +464,7 @@
 #define CLK_DIV_ACP1_VAL       ((ACP_PWI_RATIO << 5) \
                                | (ACP_G2D_RATIO << 12))
 /********************************************************/
-/* TOP Clock
+/* TOP Clock */
 /********************************************************/
 /* CLK_SRC_TOP0        */
 #define MUX_EBI_SEL         0x0                /* 0 = DOUT200, 1 = DOUT160             */
@@ -533,7 +533,7 @@
 #define CLK_DIV_G3D_VAL        0x0
 #define CLK_DIV_MFC_VAL        0x0
 /********************************************************/
-/* LEFTBUS Clock
+/* LEFTBUS Clock */
 /********************************************************/
 /* CLK_SRC_LEFTBUS     */
 #define MUX_MPLL_USER_L_SEL_SCLKMPLL          0x1
@@ -547,7 +547,7 @@
 #define CLK_DIV_LEFTBUS_VAL    ((GPL_RATIO << 4) \
                                | (GDL_RATIO))
 /********************************************************/
-/* RIGHT Clock
+/* RIGHT Clock */
 /********************************************************/
 /* CLK_SRC_RIGHTBUS    */
 #define MUX_MPLL_USER_R_SEL           0x1                              //select SLCK_MPLL