RISCV: configs: tizen_visoinfive2: Disable RISCV_ISA_V config

Visionfive2 doesn't support V extenstion.
It needs to disable its configuration.

Change-Id: I6b6ddc5b7027cdd6bd411f53df787e22e48993af
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index ec813e2..26460dd 100644 (file)
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -29,6 +29,7 @@ CONFIG_PROFILING=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_SMP=y
+# CONFIG_RISCV_ISA_V is not set
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y