arm64: dts: renesas: r8a779f0: Add L3 cache controller

Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 54474ba18f5fdcd42b00e48cdccd1d9dafc1db6e..a268617587ea4e8a1c4c6d04be5780a8f45aab5c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -23,6 +23,14 @@
                        reg = <0>;
                        device_type = "cpu";
                        power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
+                       next-level-cache = <&L3_CA55_0>;
+               };
+
+               L3_CA55_0: cache-controller-0 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779F0_PD_A2E0D0>;
+                       cache-unified;
+                       cache-level = <3>;
                };
        };