drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time

Right now CI is blacklisting module reload, so we need to be able to
enable PSR2 selective fetch in run time to test this feature before
enable it by default.
Changes in IGT will also be needed.

v2:
- Fixed handling of I915_PSR_DEBUG_ENABLE_SEL_FETCH in
intel_psr_debug_set()

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209205036.351076-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f3acc5a3c8145d754af4525deece1346e05887dc..29663db5afcd88aa2a66f3791a6b019434160d37 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1430,6 +1430,7 @@ struct intel_psr {
 #define I915_PSR_DEBUG_DISABLE         0x01
 #define I915_PSR_DEBUG_ENABLE          0x02
 #define I915_PSR_DEBUG_FORCE_PSR1      0x03
+#define I915_PSR_DEBUG_ENABLE_SEL_FETCH        0x4
 #define I915_PSR_DEBUG_IRQ             0x10
 
        u32 debug;

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index bf214d0e2dec0ecca14a5167961014df34e4cd63..43e9e362382b07ff7212f1c2b8dc9f2807f38398 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -684,7 +684,8 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
        struct intel_plane *plane;
        int i;
 
-       if (!dev_priv->params.enable_psr2_sel_fetch) {
+       if (!dev_priv->params.enable_psr2_sel_fetch &&
+           intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
                drm_dbg_kms(&dev_priv->drm,
                            "PSR2 sel fetch not enabled, disabled by parameter\n");
                return false;
@@ -1448,7 +1449,8 @@ void intel_psr_update(struct intel_dp *intel_dp,
        enable = crtc_state->has_psr;
        psr2_enable = crtc_state->has_psr2;
 
-       if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
+       if (enable == psr->enabled && psr2_enable == psr->psr2_enabled &&
+           crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) {
                /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
                if (crtc_state->crc_enabled && psr->enabled)
                        psr_force_hw_tracking_exit(intel_dp);
@@ -1637,7 +1639,7 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
        int ret;
 
        if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
-           mode > I915_PSR_DEBUG_FORCE_PSR1) {
+           mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
                drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
                return -EINVAL;
        }