[ARM] PR target/69161: Don't ignore mode when matching comparison operator in cstore...

	PR target/69161
	* config/arm/predicates.md (arm_comparison_operator_mode):
	New predicate.
	* config/arm/arm.md (*mov_scc): Use arm_comparison_operator_mode
	instead of arm_comparison_operator.
	(*mov_negscc): Likewise.
	(*mov_notscc): Likewise.
	* config/arm/thumb2.md (*thumb2_mov_scc): Likewise.
	(*thumb2_mov_negscc): Likewise.
	(*thumb2_mov_negscc_strict_it): Likewise.
	(*thumb2_mov_notscc): Likewise.
	(*thumb2_mov_notscc_strict_it): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233495 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 607b33f..5f4bd78 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2016-02-17  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/69161
+       * config/arm/predicates.md (arm_comparison_operator_mode):
+       New predicate.
+       * config/arm/arm.md (*mov_scc): Use arm_comparison_operator_mode
+       instead of arm_comparison_operator.
+       (*mov_negscc): Likewise.
+       (*mov_notscc): Likewise.
+       * config/arm/thumb2.md (*thumb2_mov_scc): Likewise.
+       (*thumb2_mov_negscc): Likewise.
+       (*thumb2_mov_negscc_strict_it): Likewise.
+       (*thumb2_mov_notscc): Likewise.
+       (*thumb2_mov_notscc_strict_it): Likewise.
+
 2016-02-17  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * config/aarch64/aarch64.c (aarch64_internal_mov_immediate):

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 64873a2..e67239d 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7175,7 +7175,7 @@
 
 (define_insn_and_split "*mov_scc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-       (match_operator:SI 1 "arm_comparison_operator"
+       (match_operator:SI 1 "arm_comparison_operator_mode"
         [(match_operand 2 "cc_register" "") (const_int 0)]))]
   "TARGET_ARM"
   "#"   ; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
@@ -7192,7 +7192,7 @@
 
 (define_insn_and_split "*mov_negscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-       (neg:SI (match_operator:SI 1 "arm_comparison_operator"
+       (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
                 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_ARM"
   "#"   ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"

diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 41a6ea4..b1cd556 100644 (file)
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -333,6 +333,13 @@
   (and (match_operand 0 "expandable_comparison_operator")
        (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
 
+;; Likewise, but don't ignore the mode.
+;; RTL SET operations require their operands source and destination have
+;; the same modes, so we can't ignore the modes there.  See PR target/69161.
+(define_predicate "arm_comparison_operator_mode"
+  (and (match_operand 0 "expandable_comparison_operator")
+       (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
+
 (define_special_predicate "lt_ge_comparison_operator"
   (match_code "lt,ge"))
 

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 39a3d80..9925365 100644 (file)
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -370,7 +370,7 @@
 
 (define_insn_and_split "*thumb2_mov_scc"
   [(set (match_operand:SI 0 "s_register_operand" "=l,r")
-       (match_operator:SI 1 "arm_comparison_operator"
+       (match_operator:SI 1 "arm_comparison_operator_mode"
         [(match_operand 2 "cc_register" "") (const_int 0)]))]
   "TARGET_THUMB2"
   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
@@ -388,7 +388,7 @@
 
 (define_insn_and_split "*thumb2_mov_negscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-       (neg:SI (match_operator:SI 1 "arm_comparison_operator"
+       (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
                 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && !arm_restrict_it"
   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
@@ -407,7 +407,7 @@
 
 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
-       (neg:SI (match_operator:SI 1 "arm_comparison_operator"
+       (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
                 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && arm_restrict_it"
   "#"   ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
@@ -436,7 +436,7 @@
 
 (define_insn_and_split "*thumb2_mov_notscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-       (not:SI (match_operator:SI 1 "arm_comparison_operator"
+       (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
                 [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && !arm_restrict_it"
   "#"   ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
@@ -456,7 +456,7 @@
 
 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
-        (not:SI (match_operator:SI 1 "arm_comparison_operator"
+       (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
   "TARGET_THUMB2 && arm_restrict_it"
   "#"   ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"