2015-06-05 Venkataramanan Kumar <venkataramanan.kumar@amd.com>

        * config/i386/sse.md (sse3_mwait): Swap the operand constriants.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224146 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a052bd3..5eb2f40 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2015-06-05  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+       * config/i386/sse.md (sse3_mwait): Swap the operand constriants.
+
 2015-06-04  DJ Delorie  <dj@redhat.com>
 
        * config/msp430/msp430.md (movsi_s): New.  Special case for

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e44ba9a..4ef51d6 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13218,10 +13218,12 @@
    (set_attr "atom_sse_attr" "fence")
    (set_attr "memory" "unknown")])
 
-
+;; As per AMD and Intel ISA manuals, the first operand is extensions
+;; and it goes to %ecx. The second operand received is hints and it goes
+;; to %eax.
 (define_insn "sse3_mwait"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
-                    (match_operand:SI 1 "register_operand" "c")]
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")
+                    (match_operand:SI 1 "register_operand" "a")]
                    UNSPECV_MWAIT)]
   "TARGET_SSE3"
 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.