if (ctx.alu_slots(n->bc.op) & AF_4SLOT)
n->flags |= NF_ALU_4SLOT;
+ if (ctx.alu_slots(n->bc.op) & AF_2SLOT)
+ n->flags |= NF_ALU_2SLOT;
+
n->src.resize(src_count);
unsigned flags = n->bc.op_ptr->flags;
alu_node *a = static_cast<alu_node*>(*I);
unsigned sflags = a->bc.slot_flags;
- if (sflags == AF_4V || (ctx.is_cayman() && sflags == AF_S)) {
+ if (sflags == AF_4V || sflags == AF_2V || (ctx.is_cayman() && sflags == AF_S)) {
if (!p)
p = sh->create_alu_packed();
a->remove();
p->push_back(a);
+ if (sflags == AF_2V && p->count() == 2) {
+ g->push_front(p);
+ p = NULL;
+ }
}
}
NF_SCHEDULE_EARLY = (1 << 9),
// for ALU_PUSH_BEFORE - when set, replace with PUSH + ALU
- NF_ALU_STACK_WORKAROUND = (1 << 10)
+ NF_ALU_STACK_WORKAROUND = (1 << 10),
+ NF_ALU_2SLOT = (1 << 11),
};
inline node_flags operator |(node_flags l, node_flags r) {
virtual bool fold_dispatch(expr_handler *ex);
unsigned forced_bank_swizzle() {
- return ((bc.op_ptr->flags & AF_INTERP) && (bc.slot_flags == AF_4V)) ?
- VEC_210 : 0;
+ return ((bc.op_ptr->flags & AF_INTERP) &&
+ ((bc.slot_flags == AF_4V) ||
+ (bc.slot_flags == AF_2V))) ? VEC_210 : 0;
}
// return param index + 1 if instruction references interpolation param,