intel/fs: print identation for control flow

INTEL_DEBUG=optimizer output changes from :

{ 10}   40: cmp.nz.f0.0(8) null:F, vgrf3470:F, 0f
{ 10}   41: (+f0.0) if(8) (null):UD,
{ 11}   42: txf_logical(8) vgrf3473:UD, vgrf250:D(null):UD, 0d(null):UD(null):UD(null):UD(null):UD, 31u, 0u(null):UD(null):UD(null):UD, 3d, 0d
{ 12}   43: and(8) vgrf262:UD, vgrf3473:UD, 2u
{ 11}   44: cmp.nz.f0.0(8) null:D, vgrf262:D, 0d
{ 10}   45: (+f0.0) if(8) (null):UD,
{ 11}   46: mov(8) vgrf270:D, -1082130432d
{ 12}   47: mov(8) vgrf271:D, 1082130432d
{ 14}   48: mov(8) vgrf274+0.0:D, 0d
{ 14}   49: mov(8) vgrf274+1.0:D, 0d

to :

{ 10}   40: cmp.nz.f0.0(8) null:F, vgrf3470:F, 0f
{ 10}   41: (+f0.0) if(8) (null):UD,
{ 11}   42:   txf_logical(8) vgrf3473:UD, vgrf250:D(null):UD, 0d(null):UD(null):UD(null):UD(null):UD, 31u, 0u(null):UD(null):UD(null):UD, 3d, 0d
{ 12}   43:   and(8) vgrf262:UD, vgrf3473:UD, 2u
{ 11}   44:   cmp.nz.f0.0(8) null:D, vgrf262:D, 0d
{ 10}   45:   (+f0.0) if(8) (null):UD,
{ 11}   46:     mov(8) vgrf270:D, -1082130432d
{ 12}   47:     mov(8) vgrf271:D, 1082130432d
{ 14}   48:     mov(8) vgrf274+0.0:D, 0d
{ 14}   49:     mov(8) vgrf274+1.0:D, 0d

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index e12e36a..ca68614 100644 (file)
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5698,11 +5698,20 @@ fs_visitor::dump_instructions_to_file(FILE *file) const
    if (cfg) {
       const register_pressure &rp = regpressure_analysis.require();
       unsigned ip = 0, max_pressure = 0;
+      unsigned cf_count = 0;
       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
+         if (inst->is_control_flow_end())
+            cf_count -= 1;
+
          max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]);
          fprintf(file, "{%3d} %4d: ", rp.regs_live_at_ip[ip], ip);
+         for (unsigned i = 0; i < cf_count; i++)
+            fprintf(file, "  ");
          dump_instruction(inst, file);
          ip++;
+
+         if (inst->is_control_flow_begin())
+            cf_count += 1;
       }
       fprintf(file, "Maximum %3d registers live at once.\n", max_pressure);
    } else {

diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h
index 1222d4d..cfe30f6 100644 (file)
--- a/src/intel/compiler/brw_ir.h
+++ b/src/intel/compiler/brw_ir.h
@@ -93,6 +93,8 @@ struct backend_instruction : public exec_node {
    bool is_3src(const struct brw_compiler *compiler) const;
    bool is_tex() const;
    bool is_math() const;
+   bool is_control_flow_begin() const;
+   bool is_control_flow_end() const;
    bool is_control_flow() const;
    bool is_commutative() const;
    bool can_do_source_mods() const;

diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index e93579f..8523c22 100644 (file)
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -889,6 +889,32 @@ backend_instruction::is_math() const
 }
 
 bool
+backend_instruction::is_control_flow_begin() const
+{
+   switch (opcode) {
+   case BRW_OPCODE_DO:
+   case BRW_OPCODE_IF:
+   case BRW_OPCODE_ELSE:
+      return true;
+   default:
+      return false;
+   }
+}
+
+bool
+backend_instruction::is_control_flow_end() const
+{
+   switch (opcode) {
+   case BRW_OPCODE_ELSE:
+   case BRW_OPCODE_WHILE:
+   case BRW_OPCODE_ENDIF:
+      return true;
+   default:
+      return false;
+   }
+}
+
+bool
 backend_instruction::is_control_flow() const
 {
    switch (opcode) {