"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"
/* When we use vector converts, we can't have input in memory. */
- if (GET_MODE (operands[0]) == DFmode && GET_MODE (operands[1]) == SImode
+ if (GET_MODE (operands[0]) == DFmode
&& TARGET_USE_VECTOR_CONVERTS && !optimize_size && TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (DFmode))
operands[1] = force_reg (SImode, operands[1]);
-
- if (GET_MODE (operands[0]) == SFmode && GET_MODE (operands[1]) == SImode
- && !optimize_size && TARGET_USE_VECTOR_CONVERTS && TARGET_SSE_MATH
- && SSE_FLOAT_MODE_P (SFmode))
+ else if (GET_MODE (operands[0]) == SFmode
+ && !optimize_size && TARGET_USE_VECTOR_CONVERTS && TARGET_SSE_MATH
+ && SSE_FLOAT_MODE_P (SFmode))
{
/* When !flag_trapping_math, we handle SImode->SFmode vector
conversions same way as SImode->DFmode.
operands[1] = tmp;
}
}
+ /* Offload operand of cvtsi2ss and cvtsi2sd into memory for
+ !TARGET_INTER_UNIT_CONVERSIONS
+ It is neccesary for the patterns to not accept nonemmory operands
+ as we would optimize out later. */
+ else if (!TARGET_INTER_UNIT_CONVERSIONS
+ && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && !optimize_size
+ && !MEM_P (operands[1]))
+ {
+ rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
+ emit_move_insn (tmp, operands[1]);
+ operands[1] = tmp;
+ }
")
(define_insn "*floatsisf2_mixed_vector"
[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m")))]
"TARGET_MIX_SSE_I387
- && (!TARGET_USE_VECTOR_CONVERTS || optimize_size)"
+ && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
+ || optimize_size)"
"@
fild%z1\t%1
#
(set_attr "amdfam10_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatsisf2_mixed_memory"
+ [(set (match_operand:SF 0 "register_operand" "=f,x")
+ (float:SF (match_operand:SI 1 "memory_operand" "m,m")))]
+ "TARGET_MIX_SSE_I387
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "@
+ fild%z1\t%1
+ cvtsi2ss\t{%1, %0|%0, %1}"
+ [(set_attr "type" "fmov,sseicvt")
+ (set_attr "mode" "SF")
+ (set_attr "athlon_decode" "*,double")
+ (set_attr "amdfam10_decode" "*,double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatsisf2_sse_vector_nointernunit"
[(set (match_operand:SF 0 "register_operand" "=x")
(float:SF (match_operand:SI 1 "memory_operand" "m")))]
[(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
"TARGET_SSE_MATH
- && (!TARGET_USE_VECTOR_CONVERTS || optimize_size)"
+ && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
+ || optimize_size)"
"cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatsisf2_sse_memory"
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (float:SF (match_operand:SI 1 "memory_operand" "m")))]
+ "TARGET_SSE_MATH
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "cvtsi2ss\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sseicvt")
+ (set_attr "mode" "SF")
+ (set_attr "athlon_decode" "double")
+ (set_attr "amdfam10_decode" "double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatsidf2_mixed_vector"
[(set (match_operand:DF 0 "register_operand" "=x,f,f")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "x,m,r")))]
[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x,!x")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m,x")))]
"TARGET_SSE2 && TARGET_MIX_SSE_I387
- && (!TARGET_USE_VECTOR_CONVERTS || !optimize_size)"
+ && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
+ || optimize_size)"
"@
fild%z1\t%1
#
(set_attr "amdfam10_decode" "*,*,vector,double,double")
(set_attr "fp_int_src" "true,true,true,true,false")])
+(define_insn "*floatsidf2_mixed_memory"
+ [(set (match_operand:DF 0 "register_operand" "=f,x")
+ (float:DF (match_operand:SI 1 "memory_operand" "m,m")))]
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "@
+ fild%z1\t%1
+ cvtsi2sd\t{%1, %0|%0, %1}"
+ [(set_attr "type" "fmov,sseicvt")
+ (set_attr "mode" "DF")
+ (set_attr "athlon_decode" "*,direct")
+ (set_attr "amdfam10_decode" "*,double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatsidf2_sse_vector"
[(set (match_operand:DF 0 "register_operand" "=x")
(float:DF (match_operand:SI 1 "register_operand" "x")))]
[(set (match_operand:DF 0 "register_operand" "=x,x,!x")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,m,x")))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && (!TARGET_USE_VECTOR_CONVERTS || optimize_size)"
+ && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
+ || optimize_size)"
"@
cvtsi2sd\t{%1, %0|%0, %1}
cvtsi2sd\t{%1, %0|%0, %1}
(set_attr "amdfam10_decode" "vector,double,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatsidf2_memory"
+ [(set (match_operand:DF 0 "register_operand" "=x")
+ (float:DF (match_operand:SI 1 "memory_operand" "x")))]
+ "TARGET_SSE2 && TARGET_SSE_MATH
+ && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
+ || optimize_size)"
+ "cvtsi2sd\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sseicvt")
+ (set_attr "mode" "DF")
+ (set_attr "athlon_decode" "direct")
+ (set_attr "amdfam10_decode" "double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatsi<mode>2_i387"
[(set (match_operand:MODEF 0 "register_operand" "=f,f")
(float:MODEF
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
"TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
- "")
+{
+ if (!TARGET_INTER_UNIT_CONVERSIONS && TARGET_64BIT
+ && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (SFmode)
+ && !optimize_size
+ && !MEM_P (operands[1]))
+ {
+ rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
+ emit_move_insn (tmp, operands[1]);
+ operands[1] = tmp;
+ }
+})
(define_insn "*floatdisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
- "TARGET_64BIT && TARGET_MIX_SSE_I387"
+ "TARGET_64BIT && TARGET_MIX_SSE_I387
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
"@
fild%z1\t%1
#
(set_attr "amdfam10_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatdisf2_mixed"
+ [(set (match_operand:SF 0 "register_operand" "=f,x")
+ (float:SF (match_operand:DI 1 "memory_operand" "m,m")))]
+ "TARGET_64BIT && TARGET_MIX_SSE_I387
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "@
+ fild%z1\t%1
+ cvtsi2ss{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "fmov,sseicvt")
+ (set_attr "mode" "SF")
+ (set_attr "athlon_decode" "*,double")
+ (set_attr "amdfam10_decode" "*,double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatdisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_64BIT && TARGET_SSE_MATH"
+ "TARGET_64BIT && TARGET_SSE_MATH
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatdisf2_memory"
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (float:SF (match_operand:DI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_SSE_MATH
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "cvtsi2ss{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sseicvt")
+ (set_attr "mode" "SF")
+ (set_attr "athlon_decode" "double")
+ (set_attr "amdfam10_decode" "double")
+ (set_attr "fp_int_src" "true")])
+
(define_expand "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
ix86_expand_convert_sign_didf_sse (operands[0], operands[1]);
DONE;
}
+ if (!TARGET_INTER_UNIT_CONVERSIONS && TARGET_64BIT
+ && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (DFmode)
+ && !optimize_size
+ && !MEM_P (operands[1]))
+ {
+ rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
+ emit_move_insn (tmp, operands[1]);
+ operands[1] = tmp;
+ }
})
(define_insn "*floatdidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
- "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
"@
fild%z1\t%1
#
(set_attr "amdfam10_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatdidf2_mixed_memory"
+ [(set (match_operand:DF 0 "register_operand" "=f,x")
+ (float:DF (match_operand:DI 1 "memory_operand" "m,m")))]
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "@
+ fild%z1\t%1
+ cvtsi2sd{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "fmov,sseicvt")
+ (set_attr "mode" "DF")
+ (set_attr "athlon_decode" "*,direct")
+ (set_attr "amdfam10_decode" "*,double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatdidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=x,x")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatdidf2_sse_memory"
+ [(set (match_operand:DF 0 "register_operand" "=x")
+ (float:DF (match_operand:DI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
+ && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
+ "cvtsi2sd{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sseicvt")
+ (set_attr "mode" "DF")
+ (set_attr "athlon_decode" "direct")
+ (set_attr "amdfam10_decode" "double")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatdi<mode>2_i387"
[(set (match_operand:MODEF 0 "register_operand" "=f,f")
(float:MODEF
(match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
- "TARGET_80387"
+ "TARGET_80387
+ && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))"
"@
fild%z1\t%1
#"