clk: renesas: r8a779g0: Add display related clocks

Add clocks related to display which are needed to get the DSI output
working.

Extracted from Renesas BSP tree.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221201095631.89448-4-tomi.valkeinen+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index ec834eb..745ff92 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
        DEF_FIXED("vcbusd2",    R8A779G0_CLK_VCBUSD2,   CLK_VC,         2, 1),
+       DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
+       DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  0x884),
 
        DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         0x870),
        DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, 0x870),
@@ -161,6 +163,11 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb1",         212,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb2",         213,    R8A779G0_CLK_S0D4_HSC),
+       DEF_MOD("dis0",         411,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("dsitxlink0",   415,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("dsitxlink1",   416,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("fcpvd0",       508,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("fcpvd1",       509,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("hscif0",       514,    R8A779G0_CLK_SASYNCPERD1),
        DEF_MOD("hscif1",       515,    R8A779G0_CLK_SASYNCPERD1),
        DEF_MOD("hscif2",       516,    R8A779G0_CLK_SASYNCPERD1),
@@ -193,6 +200,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("tmu3",         716,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tmu4",         717,    R8A779G0_CLK_SASYNCPERD2),
        DEF_MOD("tpu0",         718,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("vspd0",        830,    R8A779G0_CLK_VIOBUSD2),
+       DEF_MOD("vspd1",        831,    R8A779G0_CLK_VIOBUSD2),
        DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),
        DEF_MOD("cmt0",         910,    R8A779G0_CLK_R),
        DEF_MOD("cmt1",         911,    R8A779G0_CLK_R),