* \author Michal Krol, Karl Rasche
*/
-
#include "mtypes.h"
#include "glheader.h"
#include "context.h"
* - things from Michal's email
* + overflow on atoi
* + not-overflowing floats (don't use parse_integer..)
- * + test for 0 on matrix rows, or give a default value to parse_integer()
+ * + can remove range checking in arbparse.c
*
* - check all limits of number of various variables
* + parameters
*
* Vertex Program Stuff:
* -----------------------------------------------------
- * - ARRAY_INDEX_RELATIVE
+ * - throw an error if we mess with position and have are position invar
* - grep for XXX
*
* Mesa Stuff
instruction. Current position is stored in the output buffer in
Little-Endian convention (the lowest byte comes first). */
-
/**
* This is the text describing the rules to parse the grammar
*/
* These should match up with the values defined in arbparse.syn.h
*/
-#define REVISION 0x04
+/*
+ Changes:
+ - changed and merged V_* and F_* opcode values to OP_*.
+*/
+#define REVISION 0x05
/* program type */
#define FRAGMENT_PROGRAM 0x01
*/
#define ARB_POSITION_INVARIANT 0x20
-/* fragment program instruction class */
-#define F_ALU_INST 0x01
-#define F_TEX_INST 0x02
-
-/* fragment program instruction type */
-#define F_ALU_VECTOR 0x01
-#define F_ALU_SCALAR 0x02
-#define F_ALU_BINSC 0x03
-#define F_ALU_BIN 0x04
-#define F_ALU_TRI 0x05
-#define F_ALU_SWZ 0x06
-#define F_TEX_SAMPLE 0x07
-#define F_TEX_KIL 0x08
-
-/* vertex program instruction type */
-#define V_GEN_ARL 0x01
-#define V_GEN_VECTOR 0x02
-#define V_GEN_SCALAR 0x03
-#define V_GEN_BINSC 0x04
-#define V_GEN_BIN 0x05
-#define V_GEN_TRI 0x06
-#define V_GEN_SWZ 0x07
-
-/* fragment program instruction code */
-#define F_ABS 0x00
-#define F_ABS_SAT 0x01
-#define F_FLR 0x02
-#define F_FLR_SAT 0x03
-#define F_FRC 0x04
-#define F_FRC_SAT 0x05
-#define F_LIT 0x06
-#define F_LIT_SAT 0x07
-#define F_MOV 0x08
-#define F_MOV_SAT 0x09
-#define F_COS 0x0A
-#define F_COS_SAT 0x0B
-#define F_EX2 0x0C
-#define F_EX2_SAT 0x0D
-#define F_LG2 0x0E
-#define F_LG2_SAT 0x0F
-#define F_RCP 0x10
-#define F_RCP_SAT 0x11
-#define F_RSQ 0x12
-#define F_RSQ_SAT 0x13
-#define F_SIN 0x14
-#define F_SIN_SAT 0x15
-#define F_SCS 0x16
-#define F_SCS_SAT 0x17
-#define F_POW 0x18
-#define F_POW_SAT 0x19
-#define F_ADD 0x1A
-#define F_ADD_SAT 0x1B
-#define F_DP3 0x1C
-#define F_DP3_SAT 0x1D
-#define F_DP4 0x1E
-#define F_DP4_SAT 0x1F
-#define F_DPH 0x20
-#define F_DPH_SAT 0x21
-#define F_DST 0x22
-#define F_DST_SAT 0x23
-#define F_MAX 0x24
-#define F_MAX_SAT 0x25
-#define F_MIN 0x26
-#define F_MIN_SAT 0x27
-#define F_MUL 0x28
-#define F_MUL_SAT 0x29
-#define F_SGE 0x2A
-#define F_SGE_SAT 0x2B
-#define F_SLT 0x2C
-#define F_SLT_SAT 0x2D
-#define F_SUB 0x2E
-#define F_SUB_SAT 0x2F
-#define F_XPD 0x30
-#define F_XPD_SAT 0x31
-#define F_CMP 0x32
-#define F_CMP_SAT 0x33
-#define F_LRP 0x34
-#define F_LRP_SAT 0x35
-#define F_MAD 0x36
-#define F_MAD_SAT 0x37
-#define F_SWZ 0x38
-#define F_SWZ_SAT 0x39
-#define F_TEX 0x3A
-#define F_TEX_SAT 0x3B
-#define F_TXB 0x3C
-#define F_TXB_SAT 0x3D
-#define F_TXP 0x3E
-#define F_TXP_SAT 0x3F
-#define F_KIL 0x40
-
-/* vertex program instruction code */
-#define V_ARL 0x01
-#define V_ABS 0x02
-#define V_FLR 0x03
-#define V_FRC 0x04
-#define V_LIT 0x05
-#define V_MOV 0x06
-#define V_EX2 0x07
-#define V_EXP 0x08
-#define V_LG2 0x09
-#define V_LOG 0x0A
-#define V_RCP 0x0B
-#define V_RSQ 0x0C
-#define V_POW 0x0D
-#define V_ADD 0x0E
-#define V_DP3 0x0F
-#define V_DP4 0x10
-#define V_DPH 0x11
-#define V_DST 0x12
-#define V_MAX 0x13
-#define V_MIN 0x14
-#define V_MUL 0x15
-#define V_SGE 0x16
-#define V_SLT 0x17
-#define V_SUB 0x18
-#define V_XPD 0x19
-#define V_MAD 0x1A
-#define V_SWZ 0x1B
+/* fragment program 1.0 instruction class */
+#define OP_ALU_INST 0x00
+#define OP_TEX_INST 0x01
+
+/* vertex program 1.0 instruction class */
+/* OP_ALU_INST */
+
+/* fragment program 1.0 instruction type */
+#define OP_ALU_VECTOR 0x06
+#define OP_ALU_SCALAR 0x03
+#define OP_ALU_BINSC 0x02
+#define OP_ALU_BIN 0x01
+#define OP_ALU_TRI 0x05
+#define OP_ALU_SWZ 0x04
+#define OP_TEX_SAMPLE 0x07
+#define OP_TEX_KIL 0x08
+
+/* vertex program 1.0 instruction type */
+#define OP_ALU_ARL 0x00
+/* OP_ALU_VECTOR */
+/* OP_ALU_SCALAR */
+/* OP_ALU_BINSC */
+/* OP_ALU_BIN */
+/* OP_ALU_TRI */
+/* OP_ALU_SWZ */
+
+/* fragment program 1.0 instruction code */
+#define OP_ABS 0x00
+#define OP_ABS_SAT 0x1B
+#define OP_FLR 0x09
+#define OP_FLR_SAT 0x26
+#define OP_FRC 0x0A
+#define OP_FRC_SAT 0x27
+#define OP_LIT 0x0C
+#define OP_LIT_SAT 0x2A
+#define OP_MOV 0x11
+#define OP_MOV_SAT 0x30
+#define OP_COS 0x1F
+#define OP_COS_SAT 0x20
+#define OP_EX2 0x07
+#define OP_EX2_SAT 0x25
+#define OP_LG2 0x0B
+#define OP_LG2_SAT 0x29
+#define OP_RCP 0x14
+#define OP_RCP_SAT 0x33
+#define OP_RSQ 0x15
+#define OP_RSQ_SAT 0x34
+#define OP_SIN 0x38
+#define OP_SIN_SAT 0x39
+#define OP_SCS 0x35
+#define OP_SCS_SAT 0x36
+#define OP_POW 0x13
+#define OP_POW_SAT 0x32
+#define OP_ADD 0x01
+#define OP_ADD_SAT 0x1C
+#define OP_DP3 0x03
+#define OP_DP3_SAT 0x21
+#define OP_DP4 0x04
+#define OP_DP4_SAT 0x22
+#define OP_DPH 0x05
+#define OP_DPH_SAT 0x23
+#define OP_DST 0x06
+#define OP_DST_SAT 0x24
+#define OP_MAX 0x0F
+#define OP_MAX_SAT 0x2E
+#define OP_MIN 0x10
+#define OP_MIN_SAT 0x2F
+#define OP_MUL 0x12
+#define OP_MUL_SAT 0x31
+#define OP_SGE 0x16
+#define OP_SGE_SAT 0x37
+#define OP_SLT 0x17
+#define OP_SLT_SAT 0x3A
+#define OP_SUB 0x18
+#define OP_SUB_SAT 0x3B
+#define OP_XPD 0x1A
+#define OP_XPD_SAT 0x43
+#define OP_CMP 0x1D
+#define OP_CMP_SAT 0x1E
+#define OP_LRP 0x2B
+#define OP_LRP_SAT 0x2C
+#define OP_MAD 0x0E
+#define OP_MAD_SAT 0x2D
+#define OP_SWZ 0x19
+#define OP_SWZ_SAT 0x3C
+#define OP_TEX 0x3D
+#define OP_TEX_SAT 0x3E
+#define OP_TXB 0x3F
+#define OP_TXB_SAT 0x40
+#define OP_TXP 0x41
+#define OP_TXP_SAT 0x42
+#define OP_KIL 0x28
+
+/* vertex program 1.0 instruction code */
+#define OP_ARL 0x02
+/* OP_ABS */
+/* OP_FLR */
+/* OP_FRC */
+/* OP_LIT */
+/* OP_MOV */
+/* OP_EX2 */
+#define OP_EXP 0x08
+/* OP_LG2 */
+#define OP_LOG 0x0D
+/* OP_RCP */
+/* OP_RSQ */
+/* OP_POW */
+/* OP_ADD */
+/* OP_DP3 */
+/* OP_DP4 */
+/* OP_DPH */
+/* OP_DST */
+/* OP_MAX */
+/* OP_MIN */
+/* OP_MUL */
+/* OP_SGE */
+/* OP_SLT */
+/* OP_SUB */
+/* OP_XPD */
+/* OP_MAD */
+/* OP_SWZ */
/* fragment attribute binding */
#define FRAGMENT_ATTRIB_COLOR 0x01
parse_float (GLubyte ** inst, struct arb_program *Program)
{
GLint tmp[5], denom;
+ GLuint leading_zeros =0;
GLfloat value = 0;
#if 0
tmp[0] = parse_sign (inst); /* This is the sign of the number + - >0, - -> 1 */
#endif
tmp[1] = parse_integer (inst, Program); /* This is the integer portion of the number */
+
+ /* Now we grab the fractional portion of the number (the digits after
+ * the .). We can have leading 0's here, which parse_integer will ignore,
+ * so we'll check for those first
+ */
+ while (**inst == '0')
+ {
+ leading_zeros++;
+ (*inst)++;
+ }
tmp[2] = parse_integer (inst, Program); /* This is the fractional portion of the number */
tmp[3] = parse_sign (inst); /* This is the sign of the exponent */
tmp[4] = parse_integer (inst, Program); /* This is the exponent */
value = (GLfloat) tmp[1];
- denom = 1;
+ denom = 1;
while (denom < tmp[2])
denom *= 10;
+ denom *= _mesa_pow( 10, leading_zeros );
value += (GLfloat) tmp[2] / (GLfloat) denom;
#if 0
if (tmp[0])
return value;
}
+
/**
*/
static GLfloat
}
}
+/**
+ * \param offset The offset from the address register that we should
+ * address
+ *
+ * \return 0 on sucess, 1 on error
+ */
+static GLuint
+parse_relative_offset (GLcontext *ctx, GLubyte **inst, struct arb_program *Program,
+ GLint *offset)
+{
+ *offset = parse_integer(inst, Program);
+ if ((*offset > 63) || (*offset < -64)) {
+ _mesa_set_program_error (ctx, Program->Position,
+ "Relative offset out of range");
+ _mesa_error (ctx, GL_INVALID_OPERATION, "Relative offset %d out of range",
+ *offset);
+ return 1;
+ }
+
+ return 0;
+}
/**
* \param color 0 if color type is primary, 1 if color type is secondary
GLubyte mat = *(*inst)++;
*matrix_idx = 0;
-
+
switch (mat) {
case MATRIX_MODELVIEW:
*matrix = STATE_MODELVIEW;
/* XXX: I think this is the correct format for a matrix row */
case STATE_MATRIX_ROWS:
state_tokens[0] = STATE_MATRIX;
-
if (parse_matrix
(ctx, inst, Program, &state_tokens[1], &state_tokens[2],
&state_tokens[5]))
state_tokens[3] = parse_integer (inst, Program); /* The first row to grab */
- state_tokens[4] = parse_integer (inst, Program); /* Either the last row, 0 */
- if (state_tokens[4] == 0) {
+ if ((**inst) != 0) { /* Either the last row, 0 */
+ state_tokens[4] = parse_integer (inst, Program);
+ if (state_tokens[4] < state_tokens[3]) {
+ _mesa_set_program_error (ctx, Program->Position,
+ "Second matrix index less than the first");
+ _mesa_error (ctx, GL_INVALID_OPERATION,
+ "Second matrix index (%d) less than the first (%d)",
+ state_tokens[4], state_tokens[3]);
+ return 1;
+ }
+ }
+ else {
state_tokens[4] = state_tokens[3];
+ (*inst)++;
}
break;
}
}
else {
if (((state_tokens[1] == STATE_ENV)
- && (end_idx >= ctx->Const.MaxFragmentProgramEnvParams))
+ && (end_idx >= ctx->Const.MaxVertexProgramEnvParams))
|| ((state_tokens[1] == STATE_LOCAL)
&& (end_idx >=
- ctx->Const.MaxFragmentProgramLocalParams)))
+ ctx->Const.MaxVertexProgramLocalParams)))
out_of_range = 1;
}
if (out_of_range) {
return 0;
}
-/**
- * Handle the parsing out of a masked address register
+
+/**
+ * Handle the parsing of a address register
*
* \param Index - The register index we write to
- * \param WriteMask - The mask controlling which components we write (1->write)
*
* \return 0 on sucess, 1 on error
*/
static GLuint
-parse_masked_address_reg (GLcontext * ctx, GLubyte ** inst,
+parse_address_reg (GLcontext * ctx, GLubyte ** inst,
struct var_cache **vc_head,
- struct arb_program *Program, GLint * Index,
- GLboolean * WriteMask)
+ struct arb_program *Program, GLint * Index)
{
struct var_cache *dst;
GLuint result;
dst = parse_string (inst, vc_head, Program, &result);
Program->Position = parse_position (inst);
- /* If the name has never been added to our symbol table, we're hosed */
+ /* If the name has never been added to our symbol table, we're hosed */
if (!result) {
- _mesa_set_program_error (ctx, Program->Position, "1: Undefined variable");
- _mesa_error (ctx, GL_INVALID_OPERATION, "1: Undefined variable: %s",
+ _mesa_set_program_error (ctx, Program->Position, "Undefined variable");
+ _mesa_error (ctx, GL_INVALID_OPERATION, "Undefined variable: %s",
dst->name);
return 1;
}
return 1;
}
+ return 0;
+}
+
+/**
+ * Handle the parsing out of a masked address register
+ *
+ * \param Index - The register index we write to
+ * \param WriteMask - The mask controlling which components we write (1->write)
+ *
+ * \return 0 on sucess, 1 on error
+ */
+static GLuint
+parse_masked_address_reg (GLcontext * ctx, GLubyte ** inst,
+ struct var_cache **vc_head,
+ struct arb_program *Program, GLint * Index,
+ GLboolean * WriteMask)
+{
+ if (parse_address_reg (ctx, inst, vc_head, Program, Index))
+ return 1;
+
+ /* This should be 0x8 */
+ (*inst)++;
+
/* Writemask of .x is implied */
WriteMask[0] = 1;
WriteMask[1] = WriteMask[2] = WriteMask[3] = 0;
return 0;
}
+
/**
* Parse out a swizzle mask.
*
static GLuint
parse_src_reg (GLcontext * ctx, GLubyte ** inst, struct var_cache **vc_head,
- struct arb_program *Program, GLint * File, GLint * Index)
+ struct arb_program *Program, GLint * File, GLint * Index,
+ GLboolean *IsRelOffset )
{
struct var_cache *src;
GLuint binding_state, binding_idx, is_generic, found, offset;
*Index = src->param_binding_begin + offset;
break;
- /* XXX: */
case ARRAY_INDEX_RELATIVE:
+ {
+ GLint addr_reg_idx, rel_off;
+
+ /* First, grab the address regiseter */
+ if (parse_address_reg (ctx, inst, vc_head, Program, &addr_reg_idx))
+ return 1;
+
+ /* And the .x */
+ ((*inst)++);
+ ((*inst)++);
+ ((*inst)++);
+ ((*inst)++);
+
+ /* Then the relative offset */
+ if (parse_relative_offset(ctx, inst, Program, &rel_off)) return 1;
+
+ /* And store it properly */
+ *Index = src->param_binding_begin + rel_off;
+ *IsRelOffset = 1;
+ }
break;
}
break;
parse_vector_src_reg (GLcontext * ctx, GLubyte ** inst,
struct var_cache **vc_head, struct arb_program *Program,
GLint * File, GLint * Index, GLboolean * Negate,
- GLubyte * Swizzle)
+ GLubyte * Swizzle, GLboolean *IsRelOffset)
{
/* Grab the sign */
*Negate = parse_sign (inst);
/* And the src reg */
- if (parse_src_reg (ctx, inst, vc_head, Program, File, Index))
+ if (parse_src_reg (ctx, inst, vc_head, Program, File, Index, IsRelOffset))
return 1;
/* finally, the swizzle */
parse_scalar_src_reg (GLcontext * ctx, GLubyte ** inst,
struct var_cache **vc_head, struct arb_program *Program,
GLint * File, GLint * Index, GLboolean * Negate,
- GLubyte * Swizzle)
+ GLubyte * Swizzle, GLboolean *IsRelOffset)
{
/* Grab the sign */
*Negate = parse_sign (inst);
/* And the src reg */
- if (parse_src_reg (ctx, inst, vc_head, Program, File, Index))
+ if (parse_src_reg (ctx, inst, vc_head, Program, File, Index, IsRelOffset))
return 1;
/* Now, get the component and shove it into all the swizzle slots */
GLubyte swz[4]; /* FP's swizzle mask is a GLubyte, while VP's is GLuint */
GLuint texcoord;
GLubyte instClass, type, code;
+ GLboolean rel;
/* No condition codes in ARB_fp */
fp->UpdateCondRegister = 0;
/* Record the position in the program string for debugging */
fp->StringPos = Program->Position;
- /* F_ALU_INST or F_TEX_INST */
+ /* OP_ALU_INST or OP_TEX_INST */
instClass = *(*inst)++;
- /* F_ALU_{VECTOR, SCALAR, BINSC, BIN, TRI, SWZ},
- * F_TEX_{SAMPLE, KIL}
+ /* OP_ALU_{VECTOR, SCALAR, BINSC, BIN, TRI, SWZ},
+ * OP_TEX_{SAMPLE, KIL}
*/
type = *(*inst)++;
/* Increment the correct count */
switch (instClass) {
- case F_ALU_INST:
+ case OP_ALU_INST:
Program->NumAluInstructions++;
break;
- case F_TEX_INST:
+ case OP_TEX_INST:
Program->NumTexInstructions++;
break;
}
fp->DstReg.CondMask = COND_TR;
switch (type) {
- case F_ALU_VECTOR:
+ case OP_ALU_VECTOR:
switch (code) {
- case F_ABS_SAT:
+ case OP_ABS_SAT:
fp->Saturate = 1;
- case F_ABS:
+ case OP_ABS:
fp->Opcode = FP_OPCODE_ABS;
break;
- case F_FLR_SAT:
+ case OP_FLR_SAT:
fp->Saturate = 1;
- case F_FLR:
+ case OP_FLR:
fp->Opcode = FP_OPCODE_FLR;
break;
- case F_FRC_SAT:
+ case OP_FRC_SAT:
fp->Saturate = 1;
- case F_FRC:
+ case OP_FRC:
fp->Opcode = FP_OPCODE_FRC;
break;
- case F_LIT_SAT:
+ case OP_LIT_SAT:
fp->Saturate = 1;
- case F_LIT:
+ case OP_LIT:
fp->Opcode = FP_OPCODE_LIT;
break;
- case F_MOV_SAT:
+ case OP_MOV_SAT:
fp->Saturate = 1;
- case F_MOV:
+ case OP_MOV:
fp->Opcode = FP_OPCODE_MOV;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[0].File,
&fp->SrcReg[0].Index, &fp->SrcReg[0].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[0].Swizzle[b] = swz[b];
break;
- case F_ALU_SCALAR:
+ case OP_ALU_SCALAR:
switch (code) {
- case F_COS_SAT:
+ case OP_COS_SAT:
fp->Saturate = 1;
- case F_COS:
+ case OP_COS:
fp->Opcode = FP_OPCODE_COS;
break;
- case F_EX2_SAT:
+ case OP_EX2_SAT:
fp->Saturate = 1;
- case F_EX2:
+ case OP_EX2:
fp->Opcode = FP_OPCODE_EX2;
break;
- case F_LG2_SAT:
+ case OP_LG2_SAT:
fp->Saturate = 1;
- case F_LG2:
+ case OP_LG2:
fp->Opcode = FP_OPCODE_LG2;
break;
- case F_RCP_SAT:
+ case OP_RCP_SAT:
fp->Saturate = 1;
- case F_RCP:
+ case OP_RCP:
fp->Opcode = FP_OPCODE_RCP;
break;
- case F_RSQ_SAT:
+ case OP_RSQ_SAT:
fp->Saturate = 1;
- case F_RSQ:
+ case OP_RSQ:
fp->Opcode = FP_OPCODE_RSQ;
break;
- case F_SIN_SAT:
+ case OP_SIN_SAT:
fp->Saturate = 1;
- case F_SIN:
+ case OP_SIN:
fp->Opcode = FP_OPCODE_SIN;
break;
- case F_SCS_SAT:
+ case OP_SCS_SAT:
fp->Saturate = 1;
- case F_SCS:
+ case OP_SCS:
+
fp->Opcode = FP_OPCODE_SCS;
break;
}
if (parse_scalar_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[0].File,
&fp->SrcReg[0].Index, &fp->SrcReg[0].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[0].Swizzle[b] = swz[b];
break;
- case F_ALU_BINSC:
+ case OP_ALU_BINSC:
switch (code) {
- case F_POW_SAT:
+ case OP_POW_SAT:
fp->Saturate = 1;
- case F_POW:
+ case OP_POW:
fp->Opcode = FP_OPCODE_POW;
break;
}
if (parse_scalar_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[a].File,
&fp->SrcReg[a].Index, &fp->SrcReg[a].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[a].Swizzle[b] = swz[b];
break;
- case F_ALU_BIN:
+ case OP_ALU_BIN:
switch (code) {
- case F_ADD_SAT:
+ case OP_ADD_SAT:
fp->Saturate = 1;
- case F_ADD:
+ case OP_ADD:
fp->Opcode = FP_OPCODE_ADD;
break;
- case F_DP3_SAT:
+ case OP_DP3_SAT:
fp->Saturate = 1;
- case F_DP3:
+ case OP_DP3:
fp->Opcode = FP_OPCODE_DP3;
break;
- case F_DP4_SAT:
+ case OP_DP4_SAT:
fp->Saturate = 1;
- case F_DP4:
+ case OP_DP4:
fp->Opcode = FP_OPCODE_DP4;
break;
- case F_DPH_SAT:
+ case OP_DPH_SAT:
fp->Saturate = 1;
- case F_DPH:
+ case OP_DPH:
fp->Opcode = FP_OPCODE_DPH;
break;
- case F_DST_SAT:
+ case OP_DST_SAT:
fp->Saturate = 1;
- case F_DST:
+ case OP_DST:
fp->Opcode = FP_OPCODE_DST;
break;
- case F_MAX_SAT:
+ case OP_MAX_SAT:
fp->Saturate = 1;
- case F_MAX:
+ case OP_MAX:
fp->Opcode = FP_OPCODE_MAX;
break;
- case F_MIN_SAT:
+ case OP_MIN_SAT:
fp->Saturate = 1;
- case F_MIN:
+ case OP_MIN:
fp->Opcode = FP_OPCODE_MIN;
break;
- case F_MUL_SAT:
+ case OP_MUL_SAT:
fp->Saturate = 1;
- case F_MUL:
+ case OP_MUL:
fp->Opcode = FP_OPCODE_MUL;
break;
- case F_SGE_SAT:
+ case OP_SGE_SAT:
fp->Saturate = 1;
- case F_SGE:
+ case OP_SGE:
fp->Opcode = FP_OPCODE_SGE;
break;
- case F_SLT_SAT:
+ case OP_SLT_SAT:
fp->Saturate = 1;
- case F_SLT:
+ case OP_SLT:
fp->Opcode = FP_OPCODE_SLT;
break;
- case F_SUB_SAT:
+ case OP_SUB_SAT:
fp->Saturate = 1;
- case F_SUB:
+ case OP_SUB:
fp->Opcode = FP_OPCODE_SUB;
break;
- case F_XPD_SAT:
+ case OP_XPD_SAT:
fp->Saturate = 1;
- case F_XPD:
+ case OP_XPD:
fp->Opcode = FP_OPCODE_X2D;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[a].File,
&fp->SrcReg[a].Index, &fp->SrcReg[a].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[a].Swizzle[b] = swz[b];
}
break;
- case F_ALU_TRI:
+ case OP_ALU_TRI:
switch (code) {
- case F_CMP_SAT:
+ case OP_CMP_SAT:
fp->Saturate = 1;
- case F_CMP:
+ case OP_CMP:
fp->Opcode = FP_OPCODE_CMP;
break;
- case F_LRP_SAT:
+ case OP_LRP_SAT:
fp->Saturate = 1;
- case F_LRP:
+ case OP_LRP:
fp->Opcode = FP_OPCODE_LRP;
break;
- case F_MAD_SAT:
+ case OP_MAD_SAT:
fp->Saturate = 1;
- case F_MAD:
+ case OP_MAD:
fp->Opcode = FP_OPCODE_MAD;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[a].File,
&fp->SrcReg[a].Index, &fp->SrcReg[a].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[a].Swizzle[b] = swz[b];
}
break;
- case F_ALU_SWZ:
+ case OP_ALU_SWZ:
switch (code) {
- case F_SWZ_SAT:
+ case OP_SWZ_SAT:
fp->Saturate = 1;
- case F_SWZ:
+ case OP_SWZ:
fp->Opcode = FP_OPCODE_SWZ;
break;
}
if (parse_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[0].File,
- &fp->SrcReg[0].Index))
+ &fp->SrcReg[0].Index, &rel))
return 1;
parse_extended_swizzle_mask (inst, swz,
&fp->SrcReg[0].NegateBase);
fp->SrcReg[0].Swizzle[b] = swz[b];
break;
- case F_TEX_SAMPLE:
+ case OP_TEX_SAMPLE:
switch (code) {
- case F_TEX_SAT:
+ case OP_TEX_SAT:
fp->Saturate = 1;
- case F_TEX:
+ case OP_TEX:
fp->Opcode = FP_OPCODE_TEX;
break;
- case F_TXP_SAT:
+ case OP_TXP_SAT:
fp->Saturate = 1;
- case F_TXP:
+ case OP_TXP:
fp->Opcode = FP_OPCODE_TXP;
break;
- case F_TXB_SAT:
+ case OP_TXB_SAT:
+
fp->Saturate = 1;
- case F_TXB:
+ case OP_TXB:
fp->Opcode = FP_OPCODE_TXB;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[0].File,
&fp->SrcReg[0].Index, &fp->SrcReg[0].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[0].Swizzle[b] = swz[b];
Program->TexturesUsed[texcoord] |= fp->TexSrcBit;
break;
- case F_TEX_KIL:
+ case OP_TEX_KIL:
fp->Opcode = FP_OPCODE_KIL;
fp->SrcReg[0].Abs = GL_FALSE;
fp->SrcReg[0].NegateAbs = GL_FALSE;
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & fp->SrcReg[0].File,
&fp->SrcReg[0].Index, &fp->SrcReg[0].NegateBase,
- swz))
+ swz, &rel))
return 1;
for (b=0; b<4; b++)
fp->SrcReg[0].Swizzle[b] = swz[b];
GLint a;
GLubyte type, code;
- /* V_GEN_{ARL, VECTOR, SCALAR, BINSC, BIN, TRI, SWZ} */
+ /* OP_ALU_{ARL, VECTOR, SCALAR, BINSC, BIN, TRI, SWZ} */
type = *(*inst)++;
/* The actual opcode name */
switch (type) {
/* XXX: */
- case V_GEN_ARL:
+ case OP_ALU_ARL:
vp->Opcode = VP_OPCODE_ARL;
/* Remember to set SrcReg.RelAddr; */
return 1;
vp->DstReg.File = PROGRAM_ADDRESS;
-
/* Get a scalar src register */
if (parse_scalar_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[0].File,
&vp->SrcReg[0].Index, &vp->SrcReg[0].Negate,
- vp->SrcReg[0].Swizzle))
+ vp->SrcReg[0].Swizzle, &vp->SrcReg[0].RelAddr))
return 1;
break;
- case V_GEN_VECTOR:
+ case OP_ALU_VECTOR:
switch (code) {
- case V_ABS:
+ case OP_ABS:
vp->Opcode = VP_OPCODE_ABS;
break;
- case V_FLR:
+ case OP_FLR:
vp->Opcode = VP_OPCODE_FLR;
break;
- case V_FRC:
+ case OP_FRC:
vp->Opcode = VP_OPCODE_FRC;
break;
- case V_LIT:
+ case OP_LIT:
vp->Opcode = VP_OPCODE_LIT;
break;
- case V_MOV:
+ case OP_MOV:
vp->Opcode = VP_OPCODE_MOV;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[0].File,
&vp->SrcReg[0].Index, &vp->SrcReg[0].Negate,
- vp->SrcReg[0].Swizzle))
+ vp->SrcReg[0].Swizzle, &vp->SrcReg[0].RelAddr))
return 1;
break;
- case V_GEN_SCALAR:
+ case OP_ALU_SCALAR:
switch (code) {
- case V_EX2:
+ case OP_EX2:
vp->Opcode = VP_OPCODE_EX2;
break;
- case V_EXP:
+ case OP_EXP:
vp->Opcode = VP_OPCODE_EXP;
break;
- case V_LG2:
+ case OP_LG2:
vp->Opcode = VP_OPCODE_LG2;
break;
- case V_LOG:
+ case OP_LOG:
vp->Opcode = VP_OPCODE_LOG;
break;
- case V_RCP:
+ case OP_RCP:
vp->Opcode = VP_OPCODE_RCP;
break;
- case V_RSQ:
+ case OP_RSQ:
vp->Opcode = VP_OPCODE_RSQ;
break;
}
if (parse_scalar_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[0].File,
&vp->SrcReg[0].Index, &vp->SrcReg[0].Negate,
- vp->SrcReg[0].Swizzle))
+ vp->SrcReg[0].Swizzle, &vp->SrcReg[0].RelAddr))
return 1;
break;
- case V_GEN_BINSC:
+ case OP_ALU_BINSC:
switch (code) {
- case V_POW:
+ case OP_POW:
vp->Opcode = VP_OPCODE_POW;
break;
}
if (parse_scalar_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[a].File,
&vp->SrcReg[a].Index, &vp->SrcReg[a].Negate,
- vp->SrcReg[a].Swizzle))
+ vp->SrcReg[a].Swizzle, &vp->SrcReg[a].RelAddr))
return 1;
}
break;
- case V_GEN_BIN:
+ case OP_ALU_BIN:
switch (code) {
- case V_ADD:
+ case OP_ADD:
vp->Opcode = VP_OPCODE_ADD;
break;
- case V_DP3:
+ case OP_DP3:
vp->Opcode = VP_OPCODE_DP3;
break;
- case V_DP4:
+ case OP_DP4:
vp->Opcode = VP_OPCODE_DP4;
break;
- case V_DPH:
+ case OP_DPH:
vp->Opcode = VP_OPCODE_DPH;
break;
- case V_DST:
+ case OP_DST:
vp->Opcode = VP_OPCODE_DST;
break;
- case V_MAX:
+ case OP_MAX:
vp->Opcode = VP_OPCODE_MAX;
break;
- case V_MIN:
+ case OP_MIN:
vp->Opcode = VP_OPCODE_MIN;
break;
- case V_MUL:
+ case OP_MUL:
vp->Opcode = VP_OPCODE_MUL;
break;
- case V_SGE:
+ case OP_SGE:
vp->Opcode = VP_OPCODE_SGE;
break;
- case V_SLT:
+ case OP_SLT:
vp->Opcode = VP_OPCODE_SLT;
break;
- case V_SUB:
+ case OP_SUB:
vp->Opcode = VP_OPCODE_SUB;
break;
- case V_XPD:
+ case OP_XPD:
vp->Opcode = VP_OPCODE_XPD;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[a].File,
&vp->SrcReg[a].Index, &vp->SrcReg[a].Negate,
- vp->SrcReg[a].Swizzle))
+ vp->SrcReg[a].Swizzle, &vp->SrcReg[a].RelAddr))
return 1;
}
break;
- case V_GEN_TRI:
+ case OP_ALU_TRI:
switch (code) {
- case V_MAD:
+ case OP_MAD:
vp->Opcode = VP_OPCODE_MAD;
break;
}
if (parse_vector_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[a].File,
&vp->SrcReg[a].Index, &vp->SrcReg[a].Negate,
- vp->SrcReg[a].Swizzle))
+ vp->SrcReg[a].Swizzle, &vp->SrcReg[a].RelAddr))
return 1;
}
break;
- case V_GEN_SWZ:
+ case OP_ALU_SWZ:
switch (code) {
- case V_SWZ:
+ case OP_SWZ:
vp->Opcode = VP_OPCODE_SWZ;
break;
}
if (parse_src_reg
(ctx, inst, vc_head, Program, (GLint *) & vp->SrcReg[0].File,
- &vp->SrcReg[0].Index))
+ &vp->SrcReg[0].Index, &vp->SrcReg[0].RelAddr))
return 1;
parse_extended_swizzle_mask (inst, vp->SrcReg[0].Swizzle,
&vp->SrcReg[0].Negate);
+/*
+ * Mesa 3-D graphics library
+ * Version: 5.1
+ *
+ * Copyright (C) 1999-2003 Brian Paul All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file arbparse.c
+ * ARB_*_program parser syntax
+ * \author Michal Krole
+ */
+
+
static char arb_grammar_text[] = ".syntax program;\n"
-".emtcode REVISION 0x04\n"
+".emtcode REVISION 0x05\n"
".emtcode FRAGMENT_PROGRAM 0x01\n"
".emtcode VERTEX_PROGRAM 0x02\n"
".emtcode OPTION 0x01\n"
".emtcode ARB_FOG_EXP2 0x08\n"
".emtcode ARB_FOG_LINEAR 0x10\n"
".emtcode ARB_POSITION_INVARIANT 0x20\n"
-".emtcode F_ALU_INST 0x01\n"
-".emtcode F_TEX_INST 0x02\n"
-".emtcode F_ALU_VECTOR 0x01\n"
-".emtcode F_ALU_SCALAR 0x02\n"
-".emtcode F_ALU_BINSC 0x03\n"
-".emtcode F_ALU_BIN 0x04\n"
-".emtcode F_ALU_TRI 0x05\n"
-".emtcode F_ALU_SWZ 0x06\n"
-".emtcode F_TEX_SAMPLE 0x07\n"
-".emtcode F_TEX_KIL 0x08\n"
-".emtcode V_GEN_ARL 0x01\n"
-".emtcode V_GEN_VECTOR 0x02\n"
-".emtcode V_GEN_SCALAR 0x03\n"
-".emtcode V_GEN_BINSC 0x04\n"
-".emtcode V_GEN_BIN 0x05\n"
-".emtcode V_GEN_TRI 0x06\n"
-".emtcode V_GEN_SWZ 0x07\n"
-".emtcode F_ABS 0x00\n"
-".emtcode F_ABS_SAT 0x01\n"
-".emtcode F_FLR 0x02\n"
-".emtcode F_FLR_SAT 0x03\n"
-".emtcode F_FRC 0x04\n"
-".emtcode F_FRC_SAT 0x05\n"
-".emtcode F_LIT 0x06\n"
-".emtcode F_LIT_SAT 0x07\n"
-".emtcode F_MOV 0x08\n"
-".emtcode F_MOV_SAT 0x09\n"
-".emtcode F_COS 0x0A\n"
-".emtcode F_COS_SAT 0x0B\n"
-".emtcode F_EX2 0x0C\n"
-".emtcode F_EX2_SAT 0x0D\n"
-".emtcode F_LG2 0x0E\n"
-".emtcode F_LG2_SAT 0x0F\n"
-".emtcode F_RCP 0x10\n"
-".emtcode F_RCP_SAT 0x11\n"
-".emtcode F_RSQ 0x12\n"
-".emtcode F_RSQ_SAT 0x13\n"
-".emtcode F_SIN 0x14\n"
-".emtcode F_SIN_SAT 0x15\n"
-".emtcode F_SCS 0x16\n"
-".emtcode F_SCS_SAT 0x17\n"
-".emtcode F_POW 0x18\n"
-".emtcode F_POW_SAT 0x19\n"
-".emtcode F_ADD 0x1A\n"
-".emtcode F_ADD_SAT 0x1B\n"
-".emtcode F_DP3 0x1C\n"
-".emtcode F_DP3_SAT 0x1D\n"
-".emtcode F_DP4 0x1E\n"
-".emtcode F_DP4_SAT 0x1F\n"
-".emtcode F_DPH 0x20\n"
-".emtcode F_DPH_SAT 0x21\n"
-".emtcode F_DST 0x22\n"
-".emtcode F_DST_SAT 0x23\n"
-".emtcode F_MAX 0x24\n"
-".emtcode F_MAX_SAT 0x25\n"
-".emtcode F_MIN 0x26\n"
-".emtcode F_MIN_SAT 0x27\n"
-".emtcode F_MUL 0x28\n"
-".emtcode F_MUL_SAT 0x29\n"
-".emtcode F_SGE 0x2A\n"
-".emtcode F_SGE_SAT 0x2B\n"
-".emtcode F_SLT 0x2C\n"
-".emtcode F_SLT_SAT 0x2D\n"
-".emtcode F_SUB 0x2E\n"
-".emtcode F_SUB_SAT 0x2F\n"
-".emtcode F_XPD 0x30\n"
-".emtcode F_XPD_SAT 0x31\n"
-".emtcode F_CMP 0x32\n"
-".emtcode F_CMP_SAT 0x33\n"
-".emtcode F_LRP 0x34\n"
-".emtcode F_LRP_SAT 0x35\n"
-".emtcode F_MAD 0x36\n"
-".emtcode F_MAD_SAT 0x37\n"
-".emtcode F_SWZ 0x38\n"
-".emtcode F_SWZ_SAT 0x39\n"
-".emtcode F_TEX 0x3A\n"
-".emtcode F_TEX_SAT 0x3B\n"
-".emtcode F_TXB 0x3C\n"
-".emtcode F_TXB_SAT 0x3D\n"
-".emtcode F_TXP 0x3E\n"
-".emtcode F_TXP_SAT 0x3F\n"
-".emtcode F_KIL 0x40\n"
-".emtcode V_ARL 0x01\n"
-".emtcode V_ABS 0x02\n"
-".emtcode V_FLR 0x03\n"
-".emtcode V_FRC 0x04\n"
-".emtcode V_LIT 0x05\n"
-".emtcode V_MOV 0x06\n"
-".emtcode V_EX2 0x07\n"
-".emtcode V_EXP 0x08\n"
-".emtcode V_LG2 0x09\n"
-".emtcode V_LOG 0x0A\n"
-".emtcode V_RCP 0x0B\n"
-".emtcode V_RSQ 0x0C\n"
-".emtcode V_POW 0x0D\n"
-".emtcode V_ADD 0x0E\n"
-".emtcode V_DP3 0x0F\n"
-".emtcode V_DP4 0x10\n"
-".emtcode V_DPH 0x11\n"
-".emtcode V_DST 0x12\n"
-".emtcode V_MAX 0x13\n"
-".emtcode V_MIN 0x14\n"
-".emtcode V_MUL 0x15\n"
-".emtcode V_SGE 0x16\n"
-".emtcode V_SLT 0x17\n"
-".emtcode V_SUB 0x18\n"
-".emtcode V_XPD 0x19\n"
-".emtcode V_MAD 0x1A\n"
-".emtcode V_SWZ 0x1B\n"
+".emtcode OP_ALU_INST 0x00\n"
+".emtcode OP_TEX_INST 0x01\n"
+".emtcode OP_ALU_VECTOR 0x06\n"
+".emtcode OP_ALU_SCALAR 0x03\n"
+".emtcode OP_ALU_BINSC 0x02\n"
+".emtcode OP_ALU_BIN 0x01\n"
+".emtcode OP_ALU_TRI 0x05\n"
+".emtcode OP_ALU_SWZ 0x04\n"
+".emtcode OP_TEX_SAMPLE 0x07\n"
+".emtcode OP_TEX_KIL 0x08\n"
+".emtcode OP_ALU_ARL 0x00\n"
+".emtcode OP_ABS 0x00\n"
+".emtcode OP_ABS_SAT 0x1B\n"
+".emtcode OP_FLR 0x09\n"
+".emtcode OP_FLR_SAT 0x26\n"
+".emtcode OP_FRC 0x0A\n"
+".emtcode OP_FRC_SAT 0x27\n"
+".emtcode OP_LIT 0x0C\n"
+".emtcode OP_LIT_SAT 0x2A\n"
+".emtcode OP_MOV 0x11\n"
+".emtcode OP_MOV_SAT 0x30\n"
+".emtcode OP_COS 0x1F\n"
+".emtcode OP_COS_SAT 0x20\n"
+".emtcode OP_EX2 0x07\n"
+".emtcode OP_EX2_SAT 0x25\n"
+".emtcode OP_LG2 0x0B\n"
+".emtcode OP_LG2_SAT 0x29\n"
+".emtcode OP_RCP 0x14\n"
+".emtcode OP_RCP_SAT 0x33\n"
+".emtcode OP_RSQ 0x15\n"
+".emtcode OP_RSQ_SAT 0x34\n"
+".emtcode OP_SIN 0x38\n"
+".emtcode OP_SIN_SAT 0x39\n"
+".emtcode OP_SCS 0x35\n"
+".emtcode OP_SCS_SAT 0x36\n"
+".emtcode OP_POW 0x13\n"
+".emtcode OP_POW_SAT 0x32\n"
+".emtcode OP_ADD 0x01\n"
+".emtcode OP_ADD_SAT 0x1C\n"
+".emtcode OP_DP3 0x03\n"
+".emtcode OP_DP3_SAT 0x21\n"
+".emtcode OP_DP4 0x04\n"
+".emtcode OP_DP4_SAT 0x22\n"
+".emtcode OP_DPH 0x05\n"
+".emtcode OP_DPH_SAT 0x23\n"
+".emtcode OP_DST 0x06\n"
+".emtcode OP_DST_SAT 0x24\n"
+".emtcode OP_MAX 0x0F\n"
+".emtcode OP_MAX_SAT 0x2E\n"
+".emtcode OP_MIN 0x10\n"
+".emtcode OP_MIN_SAT 0x2F\n"
+".emtcode OP_MUL 0x12\n"
+".emtcode OP_MUL_SAT 0x31\n"
+".emtcode OP_SGE 0x16\n"
+".emtcode OP_SGE_SAT 0x37\n"
+".emtcode OP_SLT 0x17\n"
+".emtcode OP_SLT_SAT 0x3A\n"
+".emtcode OP_SUB 0x18\n"
+".emtcode OP_SUB_SAT 0x3B\n"
+".emtcode OP_XPD 0x1A\n"
+".emtcode OP_XPD_SAT 0x43\n"
+".emtcode OP_CMP 0x1D\n"
+".emtcode OP_CMP_SAT 0x1E\n"
+".emtcode OP_LRP 0x2B\n"
+".emtcode OP_LRP_SAT 0x2C\n"
+".emtcode OP_MAD 0x0E\n"
+".emtcode OP_MAD_SAT 0x2D\n"
+".emtcode OP_SWZ 0x19\n"
+".emtcode OP_SWZ_SAT 0x3C\n"
+".emtcode OP_TEX 0x3D\n"
+".emtcode OP_TEX_SAT 0x3E\n"
+".emtcode OP_TXB 0x3F\n"
+".emtcode OP_TXB_SAT 0x40\n"
+".emtcode OP_TXP 0x41\n"
+".emtcode OP_TXP_SAT 0x42\n"
+".emtcode OP_KIL 0x28\n"
+".emtcode OP_ARL 0x02\n"
+".emtcode OP_EXP 0x08\n"
+".emtcode OP_LOG 0x0D\n"
".emtcode FRAGMENT_ATTRIB_COLOR 0x01\n"
".emtcode FRAGMENT_ATTRIB_TEXCOORD 0x02\n"
".emtcode FRAGMENT_ATTRIB_FOGCOORD 0x03\n"
".errtext MISSING_FRACTION_OR_EXPONENT \"1051: missing fraction part or exponent\"\n"
".errtext MISSING_DOT_OR_EXPONENT \"1052: missing '.' or exponent\"\n"
".errtext EXPONENT_VALUE_EXPECTED \"1053: exponent value expected\"\n"
+".errtext INTEGER_OUT_OF_RANGE \"1054: integer value out of range\"\n"
"program\n"
" programs .error UNKNOWN_PROGRAM_SIGNATURE .emit REVISION;\n"
"programs\n"
"vp_statement_2\n"
" vp_namingStatement .emit DECLARATION .and semicolon;\n"
"fp_instruction\n"
-" ALUInstruction .emit F_ALU_INST .or\n"
-" TexInstruction .emit F_TEX_INST;\n"
+" ALUInstruction .emit OP_ALU_INST .or\n"
+" TexInstruction .emit OP_TEX_INST;\n"
"vp_instruction\n"
-" ARL_instruction .emit V_GEN_ARL .or\n"
-" vp_VECTORop_instruction .emit V_GEN_VECTOR .or\n"
-" vp_SCALARop_instruction .emit V_GEN_SCALAR .or\n"
-" vp_BINSCop_instruction .emit V_GEN_BINSC .or\n"
-" vp_BINop_instruction .emit V_GEN_BIN .or\n"
-" vp_TRIop_instruction .emit V_GEN_TRI .or\n"
-" vp_SWZ_instruction .emit V_GEN_SWZ;\n"
+" ARL_instruction .emit OP_ALU_ARL .or\n"
+" vp_VECTORop_instruction .emit OP_ALU_VECTOR .or\n"
+" vp_SCALARop_instruction .emit OP_ALU_SCALAR .or\n"
+" vp_BINSCop_instruction .emit OP_ALU_BINSC .or\n"
+" vp_BINop_instruction .emit OP_ALU_BIN .or\n"
+" vp_TRIop_instruction .emit OP_ALU_TRI .or\n"
+" vp_SWZ_instruction .emit OP_ALU_SWZ;\n"
"ALUInstruction\n"
-" fp_VECTORop_instruction .emit F_ALU_VECTOR .or\n"
-" fp_SCALARop_instruction .emit F_ALU_SCALAR .or\n"
-" fp_BINSCop_instruction .emit F_ALU_BINSC .or\n"
-" fp_BINop_instruction .emit F_ALU_BIN .or\n"
-" fp_TRIop_instruction .emit F_ALU_TRI .or\n"
-" fp_SWZ_instruction .emit F_ALU_SWZ;\n"
+" fp_VECTORop_instruction .emit OP_ALU_VECTOR .or\n"
+" fp_SCALARop_instruction .emit OP_ALU_SCALAR .or\n"
+" fp_BINSCop_instruction .emit OP_ALU_BINSC .or\n"
+" fp_BINop_instruction .emit OP_ALU_BIN .or\n"
+" fp_TRIop_instruction .emit OP_ALU_TRI .or\n"
+" fp_SWZ_instruction .emit OP_ALU_SWZ;\n"
"TexInstruction\n"
-" SAMPLE_instruction .emit F_TEX_SAMPLE .or\n"
-" KIL_instruction .emit F_TEX_KIL;\n"
+" SAMPLE_instruction .emit OP_TEX_SAMPLE .or\n"
+" KIL_instruction .emit OP_TEX_KIL;\n"
"ARL_instruction\n"
-" \"ARL\" .emit V_ARL .and space .and maskedAddrReg .and comma .and vp_scalarSrcReg;\n"
+" \"ARL\" .emit OP_ARL .and space .and maskedAddrReg .and comma .and vp_scalarSrcReg;\n"
"fp_VECTORop_instruction\n"
" fp_VECTORop .and space .and fp_maskedDstReg .and comma .and vectorSrcReg;\n"
"vp_VECTORop_instruction\n"
" vp_VECTORop .and space .and vp_maskedDstReg .and comma .and swizzleSrcReg;\n"
"fp_VECTORop\n"
-" \"ABS\" .emit F_ABS .or \"ABS_SAT\" .emit F_ABS_SAT .or\n"
-" \"FLR\" .emit F_FLR .or \"FLR_SAT\" .emit F_FLR_SAT .or\n"
-" \"FRC\" .emit F_FRC .or \"FRC_SAT\" .emit F_FRC_SAT .or\n"
-" \"LIT\" .emit F_LIT .or \"LIT_SAT\" .emit F_LIT_SAT .or\n"
-" \"MOV\" .emit F_MOV .or \"MOV_SAT\" .emit F_MOV_SAT;\n"
+" \"ABS\" .emit OP_ABS .or \"ABS_SAT\" .emit OP_ABS_SAT .or\n"
+" \"FLR\" .emit OP_FLR .or \"FLR_SAT\" .emit OP_FLR_SAT .or\n"
+" \"FRC\" .emit OP_FRC .or \"FRC_SAT\" .emit OP_FRC_SAT .or\n"
+" \"LIT\" .emit OP_LIT .or \"LIT_SAT\" .emit OP_LIT_SAT .or\n"
+" \"MOV\" .emit OP_MOV .or \"MOV_SAT\" .emit OP_MOV_SAT;\n"
"vp_VECTORop\n"
-" \"ABS\" .emit V_ABS .or\n"
-" \"FLR\" .emit V_FLR .or\n"
-" \"FRC\" .emit V_FRC .or\n"
-" \"LIT\" .emit V_LIT .or\n"
-" \"MOV\" .emit V_MOV;\n"
+" \"ABS\" .emit OP_ABS .or\n"
+" \"FLR\" .emit OP_FLR .or\n"
+" \"FRC\" .emit OP_FRC .or\n"
+" \"LIT\" .emit OP_LIT .or\n"
+" \"MOV\" .emit OP_MOV;\n"
"fp_SCALARop_instruction\n"
" fp_SCALARop .and space .and fp_maskedDstReg .and comma .and fp_scalarSrcReg;\n"
"vp_SCALARop_instruction\n"
" vp_SCALARop .and space .and vp_maskedDstReg .and comma .and vp_scalarSrcReg;\n"
"fp_SCALARop\n"
-" \"COS\" .emit F_COS .or \"COS_SAT\" .emit F_COS_SAT .or\n"
-" \"EX2\" .emit F_EX2 .or \"EX2_SAT\" .emit F_EX2_SAT .or\n"
-" \"LG2\" .emit F_LG2 .or \"LG2_SAT\" .emit F_LG2_SAT .or\n"
-" \"RCP\" .emit F_RCP .or \"RCP_SAT\" .emit F_RCP_SAT .or\n"
-" \"RSQ\" .emit F_RSQ .or \"RSQ_SAT\" .emit F_RSQ_SAT .or\n"
-" \"SIN\" .emit F_SIN .or \"SIN_SAT\" .emit F_SIN_SAT .or\n"
-" \"SCS\" .emit F_SCS .or \"SCS_SAT\" .emit F_SCS_SAT;\n"
+" \"COS\" .emit OP_COS .or \"COS_SAT\" .emit OP_COS_SAT .or\n"
+" \"EX2\" .emit OP_EX2 .or \"EX2_SAT\" .emit OP_EX2_SAT .or\n"
+" \"LG2\" .emit OP_LG2 .or \"LG2_SAT\" .emit OP_LG2_SAT .or\n"
+" \"RCP\" .emit OP_RCP .or \"RCP_SAT\" .emit OP_RCP_SAT .or\n"
+" \"RSQ\" .emit OP_RSQ .or \"RSQ_SAT\" .emit OP_RSQ_SAT .or\n"
+" \"SIN\" .emit OP_SIN .or \"SIN_SAT\" .emit OP_SIN_SAT .or\n"
+" \"SCS\" .emit OP_SCS .or \"SCS_SAT\" .emit OP_SCS_SAT;\n"
"vp_SCALARop\n"
-" \"EX2\" .emit V_EX2 .or\n"
-" \"EXP\" .emit V_EXP .or\n"
-" \"LG2\" .emit V_LG2 .or\n"
-" \"LOG\" .emit V_LOG .or\n"
-" \"RCP\" .emit V_RCP .or\n"
-" \"RSQ\" .emit V_RSQ;\n"
+" \"EX2\" .emit OP_EX2 .or\n"
+" \"EXP\" .emit OP_EXP .or\n"
+" \"LG2\" .emit OP_LG2 .or\n"
+" \"LOG\" .emit OP_LOG .or\n"
+" \"RCP\" .emit OP_RCP .or\n"
+" \"RSQ\" .emit OP_RSQ;\n"
"fp_BINSCop_instruction\n"
" fp_BINSCop .and space .and fp_maskedDstReg .and comma .and fp_scalarSrcReg .and comma .and\n"
" fp_scalarSrcReg;\n"
" vp_BINSCop .and space .and vp_maskedDstReg .and comma .and vp_scalarSrcReg .and comma .and\n"
" vp_scalarSrcReg;\n"
"fp_BINSCop\n"
-" \"POW\" .emit F_POW .or \"POW_SAT\" .emit F_POW_SAT;\n"
+" \"POW\" .emit OP_POW .or \"POW_SAT\" .emit OP_POW_SAT;\n"
"vp_BINSCop\n"
-" \"POW\" .emit V_POW;\n"
+" \"POW\" .emit OP_POW;\n"
"fp_BINop_instruction\n"
" fp_BINop .and space .and fp_maskedDstReg .and comma .and vectorSrcReg .and comma .and\n"
" vectorSrcReg;\n"
" vp_BINop .and space .and vp_maskedDstReg .and comma .and swizzleSrcReg .and comma .and\n"
" swizzleSrcReg;\n"
"fp_BINop\n"
-" \"ADD\" .emit F_ADD .or \"ADD_SAT\" .emit F_ADD_SAT .or\n"
-" \"DP3\" .emit F_DP3 .or \"DP3_SAT\" .emit F_DP3_SAT .or\n"
-" \"DP4\" .emit F_DP4 .or \"DP4_SAT\" .emit F_DP4_SAT .or\n"
-" \"DPH\" .emit F_DPH .or \"DPH_SAT\" .emit F_DPH_SAT .or\n"
-" \"DST\" .emit F_DST .or \"DST_SAT\" .emit F_DST_SAT .or\n"
-" \"MAX\" .emit F_MAX .or \"MAX_SAT\" .emit F_MAX_SAT .or\n"
-" \"MIN\" .emit F_MIN .or \"MIN_SAT\" .emit F_MIN_SAT .or\n"
-" \"MUL\" .emit F_MUL .or \"MUL_SAT\" .emit F_MUL_SAT .or\n"
-" \"SGE\" .emit F_SGE .or \"SGE_SAT\" .emit F_SGE_SAT .or\n"
-" \"SLT\" .emit F_SLT .or \"SLT_SAT\" .emit F_SLT_SAT .or\n"
-" \"SUB\" .emit F_SUB .or \"SUB_SAT\" .emit F_SUB_SAT .or\n"
-" \"XPD\" .emit F_XPD .or \"XPD_SAT\" .emit F_XPD_SAT;\n"
+" \"ADD\" .emit OP_ADD .or \"ADD_SAT\" .emit OP_ADD_SAT .or\n"
+" \"DP3\" .emit OP_DP3 .or \"DP3_SAT\" .emit OP_DP3_SAT .or\n"
+" \"DP4\" .emit OP_DP4 .or \"DP4_SAT\" .emit OP_DP4_SAT .or\n"
+" \"DPH\" .emit OP_DPH .or \"DPH_SAT\" .emit OP_DPH_SAT .or\n"
+" \"DST\" .emit OP_DST .or \"DST_SAT\" .emit OP_DST_SAT .or\n"
+" \"MAX\" .emit OP_MAX .or \"MAX_SAT\" .emit OP_MAX_SAT .or\n"
+" \"MIN\" .emit OP_MIN .or \"MIN_SAT\" .emit OP_MIN_SAT .or\n"
+" \"MUL\" .emit OP_MUL .or \"MUL_SAT\" .emit OP_MUL_SAT .or\n"
+" \"SGE\" .emit OP_SGE .or \"SGE_SAT\" .emit OP_SGE_SAT .or\n"
+" \"SLT\" .emit OP_SLT .or \"SLT_SAT\" .emit OP_SLT_SAT .or\n"
+" \"SUB\" .emit OP_SUB .or \"SUB_SAT\" .emit OP_SUB_SAT .or\n"
+" \"XPD\" .emit OP_XPD .or \"XPD_SAT\" .emit OP_XPD_SAT;\n"
"vp_BINop\n"
-" \"ADD\" .emit V_ADD .or\n"
-" \"DP3\" .emit V_DP3 .or\n"
-" \"DP4\" .emit V_DP4 .or\n"
-" \"DPH\" .emit V_DPH .or\n"
-" \"DST\" .emit V_DST .or\n"
-" \"MAX\" .emit V_MAX .or\n"
-" \"MIN\" .emit V_MIN .or\n"
-" \"MUL\" .emit V_MUL .or\n"
-" \"SGE\" .emit V_SGE .or\n"
-" \"SLT\" .emit V_SLT .or\n"
-" \"SUB\" .emit V_SUB .or\n"
-" \"XPD\" .emit V_XPD;\n"
+" \"ADD\" .emit OP_ADD .or\n"
+" \"DP3\" .emit OP_DP3 .or\n"
+" \"DP4\" .emit OP_DP4 .or\n"
+" \"DPH\" .emit OP_DPH .or\n"
+" \"DST\" .emit OP_DST .or\n"
+" \"MAX\" .emit OP_MAX .or\n"
+" \"MIN\" .emit OP_MIN .or\n"
+" \"MUL\" .emit OP_MUL .or\n"
+" \"SGE\" .emit OP_SGE .or\n"
+" \"SLT\" .emit OP_SLT .or\n"
+" \"SUB\" .emit OP_SUB .or\n"
+" \"XPD\" .emit OP_XPD;\n"
"fp_TRIop_instruction\n"
" fp_TRIop .and space .and fp_maskedDstReg .and comma .and vectorSrcReg .and comma .and\n"
" vectorSrcReg .and comma .and vectorSrcReg;\n"
" vp_TRIop .and space .and vp_maskedDstReg .and comma .and swizzleSrcReg .and comma .and\n"
" swizzleSrcReg .and comma .and swizzleSrcReg;\n"
"fp_TRIop\n"
-" \"CMP\" .emit F_CMP .or \"CMP_SAT\" .emit F_CMP_SAT .or\n"
-" \"LRP\" .emit F_LRP .or \"LRP_SAT\" .emit F_LRP_SAT .or\n"
-" \"MAD\" .emit F_MAD .or \"MAD_SAT\" .emit F_MAD_SAT;\n"
+" \"CMP\" .emit OP_CMP .or \"CMP_SAT\" .emit OP_CMP_SAT .or\n"
+" \"LRP\" .emit OP_LRP .or \"LRP_SAT\" .emit OP_LRP_SAT .or\n"
+" \"MAD\" .emit OP_MAD .or \"MAD_SAT\" .emit OP_MAD_SAT;\n"
"vp_TRIop\n"
-" \"MAD\" .emit V_MAD;\n"
+" \"MAD\" .emit OP_MAD;\n"
"fp_SWZ_instruction\n"
" SWZop .and space .and fp_maskedDstReg .and comma .and fp_srcReg .and comma .and\n"
" fp_extendedSwizzle .error EXT_SWIZ_COMP_EXPECTED;\n"
"vp_SWZ_instruction\n"
-" \"SWZ\" .emit V_SWZ .and space .and vp_maskedDstReg .and comma .and vp_srcReg .and comma .and\n"
+" \"SWZ\" .emit OP_SWZ .and space .and vp_maskedDstReg .and comma .and vp_srcReg .and comma .and\n"
" vp_extendedSwizzle .error EXT_SWIZ_COMP_EXPECTED;\n"
"SWZop\n"
-" \"SWZ\" .emit F_SWZ .or \"SWZ_SAT\" .emit F_SWZ_SAT;\n"
+" \"SWZ\" .emit OP_SWZ .or \"SWZ_SAT\" .emit OP_SWZ_SAT;\n"
"SAMPLE_instruction\n"
" SAMPLEop .and space .and fp_maskedDstReg .and comma .and vectorSrcReg .and comma .and\n"
" texImageUnit .and comma .and texTarget .error TEX_TARGET_EXPECTED;\n"
"SAMPLEop\n"
-" \"TEX\" .emit F_TEX .or \"TEX_SAT\" .emit F_TEX_SAT .or\n"
-" \"TXB\" .emit F_TXB .or \"TXB_SAT\" .emit F_TXB_SAT .or\n"
-" \"TXP\" .emit F_TXP .or \"TXP_SAT\" .emit F_TXP_SAT;\n"
+" \"TEX\" .emit OP_TEX .or \"TEX_SAT\" .emit OP_TEX_SAT .or\n"
+" \"TXB\" .emit OP_TXB .or \"TXB_SAT\" .emit OP_TXB_SAT .or\n"
+" \"TXP\" .emit OP_TXP .or \"TXP_SAT\" .emit OP_TXP_SAT;\n"
"KIL_instruction\n"
-" \"KIL\" .emit F_KIL .and space .and vectorSrcReg;\n"
+" \"KIL\" .emit OP_KIL .and space .and vectorSrcReg;\n"
"texImageUnit\n"
" \"texture\" .error TEXTURE_EXPECTED .and optTexImageUnitNum;\n"
"texTarget\n"
"progParamArrayMem\n"
" progParamArrayAbs .or progParamArrayRel;\n"
"progParamArrayAbs\n"
-" integer .emit ARRAY_INDEX_ABSOLUTE;\n"
+" integer_ne .emit ARRAY_INDEX_ABSOLUTE;\n"
"progParamArrayRel\n"
" addrReg .emit ARRAY_INDEX_RELATIVE .and addrComponent .and addrRegRelOffset;\n"
"addrRegRelOffset\n"
" \"XPD\" .or \"program\" .or \"result\" .or \"state\" .or \"vertex\";\n"
"integer\n"
" integer_ne .error INTEGER_EXPECTED;\n"
+"zero\n"
+" '0';\n"
+"leading_zeroes\n"
+" .loop zero;\n"
+"no_digit\n"
+" no_digit_1 .or .true;\n"
+"no_digit_1\n"
+" digit10 .and .false .error INTEGER_OUT_OF_RANGE;\n"
+"all_zeroes\n"
+" all_zeroes_1 .or no_digit_1;\n"
+"all_zeroes_1\n"
+" '0' .and .loop zero .and no_digit;\n"
"integer_0_3\n"
-" integer;\n"
+" integer_0_3_1 .error INTEGER_EXPECTED .and .true .emit 0x00 .emit $;\n"
+"integer_0_3_1\n"
+" integer_0_3_2 .or all_zeroes .emit '0';\n"
+"integer_0_3_2 \n"
+" leading_zeroes .and '1'-'3' .emit * .and no_digit;\n"
"integer_0_63\n"
-" integer;\n"
+" integer_0_63_1 .error INTEGER_EXPECTED .and .true .emit 0x00 .emit $;\n"
+"integer_0_63_1\n"
+" integer_0_63_2 .or integer_0_63_3 .or integer_0_63_4 .or integer_0_63_5 .or\n"
+" all_zeroes .emit '0';\n"
+"integer_0_63_2 \n"
+" leading_zeroes .and '7'-'9' .emit * .and no_digit;\n"
+"integer_0_63_3 \n"
+" leading_zeroes .and '1'-'5' .emit * .and '0'-'9' .emit * .and no_digit;\n"
+"integer_0_63_4 \n"
+" leading_zeroes .and '6' .emit * .and '0'-'3' .emit * .and no_digit;\n"
+"integer_0_63_5 \n"
+" leading_zeroes .and '1'-'6' .emit * .and no_digit;\n"
"integer_0_64\n"
-" integer;\n"
+" integer_0_64_1 .error INTEGER_EXPECTED .and .true .emit 0x00 .emit $;\n"
+"integer_0_64_1\n"
+" integer_0_64_2 .or integer_0_64_3 .or integer_0_64_4 .or integer_0_64_5 .or\n"
+" all_zeroes .emit '0';\n"
+"integer_0_64_2 \n"
+" leading_zeroes .and '7'-'9' .emit * .and no_digit;\n"
+"integer_0_64_3 \n"
+" leading_zeroes .and '1'-'5' .emit * .and '0'-'9' .emit * .and no_digit;\n"
+"integer_0_64_4 \n"
+" leading_zeroes .and '6' .emit * .and '0'-'4' .emit * .and no_digit;\n"
+"integer_0_64_5 \n"
+" leading_zeroes .and '1'-'6' .emit * .and no_digit;\n"
"optional_space\n"
" space .or .true;\n"
"space\n"
"float_5\n"
" exponent .emit 0x00;\n"
"float_legacy\n"
-" integer_ne .and .true .emit 0x00 .emit '1' .emit 0x00 .emit $;\n"
+" integer_ne .and .true .emit 0x00 .emit 0x00;\n"
"integer_ne\n"
" integer_ne_1 .and .true .emit 0x00 .emit $;\n"
"integer_ne_1\n"
"optional_integer\n"
" integer_ne .or .true .emit 0x00;\n"
"optional_exponent\n"
-" exponent .or .true .emit '1' .emit 0x00 .emit $;\n"
+" exponent .or .true .emit 0x00;\n"
"exponent\n"
" exponent_1 .and optional_sign_ne .and integer_ne .error EXPONENT_VALUE_EXPECTED;\n"
"exponent_1\n"
projects / platform / upstream / mesa.git / commitdiff