*/
#include "i915_drv.h"
+#include "gvt.h"
#define MB_TO_BYTES(mb) ((mb) << 20ULL)
#define BYTES_TO_MB(b) ((b) >> 20ULL)
*/
#include "i915_drv.h"
+#include "gvt.h"
enum {
INTEL_GVT_PCI_BAR_GTTMMIO = 0,
#include <linux/slab.h>
#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
#include "trace.h"
#define INVALID_OP (~0U)
*/
#include "i915_drv.h"
+#include "gvt.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)
{
*/
#include "i915_drv.h"
+#include "gvt.h"
#define GMBUS1_TOTAL_BYTES_SHIFT 16
#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
*/
#include "i915_drv.h"
+#include "gvt.h"
#define _EL_OFFSET_STATUS 0x234
#define _EL_OFFSET_STATUS_BUF 0x370
#include <linux/crc32.h>
#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
#define FIRMWARE_VERSION (0x0)
*/
#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
#include "trace.h"
static bool enable_out_of_sync = false;
#include <linux/kthread.h>
#include "i915_drv.h"
+#include "gvt.h"
struct intel_gvt_host intel_gvt_host;
*/
void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
{
- struct intel_gvt *gvt = &dev_priv->gvt;
+ struct intel_gvt *gvt = to_gvt(dev_priv);
- if (WARN_ON(!gvt->initialized))
+ if (WARN_ON(!gvt))
return;
clean_service_thread(gvt);
intel_gvt_clean_mmio_info(gvt);
intel_gvt_free_firmware(gvt);
- gvt->initialized = false;
+ kfree(dev_priv->gvt);
+ dev_priv->gvt = NULL;
}
/**
*/
int intel_gvt_init_device(struct drm_i915_private *dev_priv)
{
- struct intel_gvt *gvt = &dev_priv->gvt;
+ struct intel_gvt *gvt;
int ret;
/*
if (WARN_ON(!intel_gvt_host.initialized))
return -EINVAL;
- if (WARN_ON(gvt->initialized))
+ if (WARN_ON(dev_priv->gvt))
return -EEXIST;
+ gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL);
+ if (!gvt)
+ return -ENOMEM;
+
gvt_dbg_core("init gvt device\n");
mutex_init(&gvt->lock);
goto out_clean_cmd_parser;
gvt_dbg_core("gvt device creation is done\n");
- gvt->initialized = true;
+ dev_priv->gvt = gvt;
return 0;
out_clean_cmd_parser:
intel_gvt_free_firmware(gvt);
out_clean_mmio_info:
intel_gvt_clean_mmio_info(gvt);
+ kfree(gvt);
return ret;
}
struct intel_gvt {
struct mutex lock;
- bool initialized;
-
struct drm_i915_private *dev_priv;
struct idr vgpu_idr; /* vGPU IDR pool */
unsigned long service_request;
};
+static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
+{
+ return i915->gvt;
+}
+
enum {
INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
};
*/
#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
/* XXX FIXME i915 has changed PP_XXX definition */
#define PCH_PP_STATUS _MMIO(0xc7200)
*/
#include "i915_drv.h"
+#include "gvt.h"
/* common offset among interrupt control registers */
#define regbase_to_isr(base) (base)
*/
#include "i915_drv.h"
+#include "gvt.h"
/**
* intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
#include <linux/acpi.h>
#include "i915_drv.h"
+#include "gvt.h"
static int init_vgpu_opregion(struct intel_vgpu *vgpu, u32 gpa)
{
*/
#include "i915_drv.h"
+#include "gvt.h"
struct render_mmio {
int ring_id;
*/
#include "i915_drv.h"
+#include "gvt.h"
static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu)
{
*
*/
-#include "i915_drv.h"
-
#include <linux/kthread.h>
+#include "i915_drv.h"
+#include "gvt.h"
+
#define RING_CTX_OFF(x) \
offsetof(struct execlist_ring_context, x)
*/
#include "i915_drv.h"
+#include "gvt.h"
+#include "i915_pvinfo.h"
static void clean_vgpu_mmio(struct intel_vgpu *vgpu)
{
struct i915_virtual_gpu vgpu;
- struct intel_gvt gvt;
+ struct intel_gvt *gvt;
struct intel_guc guc;
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
- return dev_priv->gvt.initialized;
+ return dev_priv->gvt;
}
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
#ifndef _INTEL_GVT_H_
#define _INTEL_GVT_H_
-#include "i915_pvinfo.h"
-#include "gvt/gvt.h"
+struct intel_gvt;
#ifdef CONFIG_DRM_I915_GVT
int intel_gvt_init(struct drm_i915_private *dev_priv);