crypto: octeontx2 - parameters for custom engine groups

Added devlink parameters to create and delete custom CPT engine groups.

Example:
devlink dev param set pci/0002:20:00.0 name egrp_create value \
                "se:32;se.out" cmode runtime
devlink dev param set pci/0002:20:00.0 name egrp_delete value \
                "egrp:1" cmode runtime

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/marvell/octeontx2/Makefile b/drivers/crypto/marvell/octeontx2/Makefile
index c242d22..965297e 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/Makefile
+++ b/drivers/crypto/marvell/octeontx2/Makefile
@@ -3,7 +3,7 @@ obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += rvu_cptpf.o rvu_cptvf.o
 
 rvu_cptpf-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \
                  otx2_cpt_mbox_common.o otx2_cptpf_ucode.o otx2_cptlf.o \
-                 cn10k_cpt.o
+                 cn10k_cpt.o otx2_cpt_devlink.o
 rvu_cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \
                  otx2_cpt_mbox_common.o otx2_cptvf_reqmgr.o \
                  otx2_cptvf_algs.o cn10k_cpt.o

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
index c5445b0..fb56824 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/crypto.h>
+#include <net/devlink.h>
 #include "otx2_cpt_hw_types.h"
 #include "rvu.h"
 #include "mbox.h"

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
new file mode 100644 (file)
index 0000000..bb02e0d
--- /dev/null
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2021 Marvell. */
+
+#include "otx2_cpt_devlink.h"
+
+static int otx2_cpt_dl_egrp_create(struct devlink *dl, u32 id,
+                                  struct devlink_param_gset_ctx *ctx)
+{
+       struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
+       struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
+
+       return otx2_cpt_dl_custom_egrp_create(cptpf, ctx);
+}
+
+static int otx2_cpt_dl_egrp_delete(struct devlink *dl, u32 id,
+                                  struct devlink_param_gset_ctx *ctx)
+{
+       struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
+       struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
+
+       return otx2_cpt_dl_custom_egrp_delete(cptpf, ctx);
+}
+
+static int otx2_cpt_dl_uc_info(struct devlink *dl, u32 id,
+                              struct devlink_param_gset_ctx *ctx)
+{
+       struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);
+       struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf;
+
+       otx2_cpt_print_uc_dbg_info(cptpf);
+
+       return 0;
+}
+
+enum otx2_cpt_dl_param_id {
+       OTX2_CPT_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
+       OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE,
+       OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE,
+};
+
+static const struct devlink_param otx2_cpt_dl_params[] = {
+       DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE,
+                            "egrp_create", DEVLINK_PARAM_TYPE_STRING,
+                            BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+                            otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_create,
+                            NULL),
+       DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE,
+                            "egrp_delete", DEVLINK_PARAM_TYPE_STRING,
+                            BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+                            otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_delete,
+                            NULL),
+};
+
+static int otx2_cpt_devlink_info_get(struct devlink *devlink,
+                                    struct devlink_info_req *req,
+                                    struct netlink_ext_ack *extack)
+{
+       return devlink_info_driver_name_put(req, "rvu_cptpf");
+}
+
+static const struct devlink_ops otx2_cpt_devlink_ops = {
+       .info_get = otx2_cpt_devlink_info_get,
+};
+
+int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf)
+{
+       struct device *dev = &cptpf->pdev->dev;
+       struct otx2_cpt_devlink *cpt_dl;
+       struct devlink *dl;
+       int ret;
+
+       dl = devlink_alloc(&otx2_cpt_devlink_ops,
+                          sizeof(struct otx2_cpt_devlink), dev);
+       if (!dl) {
+               dev_warn(dev, "devlink_alloc failed\n");
+               return -ENOMEM;
+       }
+
+       cpt_dl = devlink_priv(dl);
+       cpt_dl->dl = dl;
+       cpt_dl->cptpf = cptpf;
+       cptpf->dl = dl;
+       ret = devlink_params_register(dl, otx2_cpt_dl_params,
+                                     ARRAY_SIZE(otx2_cpt_dl_params));
+       if (ret) {
+               dev_err(dev, "devlink params register failed with error %d",
+                       ret);
+               devlink_free(dl);
+               return ret;
+       }
+
+       devlink_register(dl);
+
+       return 0;
+}
+
+void otx2_cpt_unregister_dl(struct otx2_cptpf_dev *cptpf)
+{
+       struct devlink *dl = cptpf->dl;
+
+       if (!dl)
+               return;
+
+       devlink_unregister(dl);
+       devlink_params_unregister(dl, otx2_cpt_dl_params,
+                                 ARRAY_SIZE(otx2_cpt_dl_params));
+       devlink_free(dl);
+}

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.h
new file mode 100644 (file)
index 0000000..8b7d88c
--- /dev/null
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ * Copyright (C) 2021 Marvell.
+ */
+
+#ifndef __OTX2_CPT_DEVLINK_H
+#define __OTX2_CPT_DEVLINK_H
+
+#include "otx2_cpt_common.h"
+#include "otx2_cptpf.h"
+
+struct otx2_cpt_devlink {
+       struct devlink *dl;
+       struct otx2_cptpf_dev *cptpf;
+};
+
+/* Devlink APIs */
+int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf);
+void otx2_cpt_unregister_dl(struct otx2_cptpf_dev *cptpf);
+
+#endif /* __OTX2_CPT_DEVLINK_H */

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf.h b/drivers/crypto/marvell/octeontx2/otx2_cptpf.h
index 5ebba86..05b2d9c 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf.h
@@ -53,6 +53,9 @@ struct otx2_cptpf_dev {
        u8 enabled_vfs;         /* Number of enabled VFs */
        u8 kvf_limits;          /* Kernel crypto limits */
        bool has_cpt1;
+
+       /* Devlink */
+       struct devlink *dl;
 };
 
 irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
index be1ad55..1720a5b 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
@@ -4,6 +4,7 @@
 #include <linux/firmware.h>
 #include "otx2_cpt_hw_types.h"
 #include "otx2_cpt_common.h"
+#include "otx2_cpt_devlink.h"
 #include "otx2_cptpf_ucode.h"
 #include "otx2_cptpf.h"
 #include "cn10k_cpt.h"
@@ -766,8 +767,15 @@ static int otx2_cptpf_probe(struct pci_dev *pdev,
        err = sysfs_create_group(&dev->kobj, &cptpf_sysfs_group);
        if (err)
                goto cleanup_eng_grps;
+
+       err = otx2_cpt_register_dl(cptpf);
+       if (err)
+               goto sysfs_grp_del;
+
        return 0;
 
+sysfs_grp_del:
+       sysfs_remove_group(&dev->kobj, &cptpf_sysfs_group);
 cleanup_eng_grps:
        otx2_cpt_cleanup_eng_grps(pdev, &cptpf->eng_grps);
 unregister_intr:
@@ -787,6 +795,7 @@ static void otx2_cptpf_remove(struct pci_dev *pdev)
                return;
 
        cptpf_sriov_disable(pdev);
+       otx2_cpt_unregister_dl(cptpf);
        /* Delete sysfs entry created for kernel VF limits */
        sysfs_remove_group(&pdev->dev.kobj, &cptpf_sysfs_group);
        /* Cleanup engine groups */