drivers: pci: Support 64bit prefetchable MMIO range.

Verification has been completed on NVIDIA GT710 with modetest.

Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 152c715..def9d00 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1506,7 +1506,8 @@
                        device_type = "pci";
                        starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
                        bus-range = <0x0 0xff>;
-                       ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>;
+                       ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
                        msi-parent = <&plic>;
                        interrupts = <56>;
                        interrupt-controller;
@@ -1544,7 +1545,8 @@
                        device_type = "pci";
                        starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
                        bus-range = <0x0 0xff>;
-                       ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>;
+                       ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
                        msi-parent = <&plic>;
                        interrupts = <57>;
                        interrupt-controller;

diff --git a/drivers/pci/controller/pcie-plda.c b/drivers/pci/controller/pcie-plda.c
index db966f4..92794b8 100644 (file)
--- a/drivers/pci/controller/pcie-plda.c
+++ b/drivers/pci/controller/pcie-plda.c
@@ -41,6 +41,7 @@
 #define ISTATUS_MSI                    0x194
 #define CFG_SPACE                      0x1000
 #define GEN_SETTINGS                   0x80
+#define PCIE_WINROM                    0xFC
 #define PMSG_SUPPORT_RX                        0x3F0
 
 #define PCI_MISC                       0xB4
@@ -48,6 +49,7 @@
 #define PLDA_EP_ENABLE                 0
 #define PLDA_RP_ENABLE                 1
 
+#define PREF_MEM_WIN_64_SUPPORT                BIT(3)
 #define PMSG_LTR_SUPPORT               BIT(2)
 #define PDLA_LINK_SPEED_GEN2           BIT(12)
 #define PLDA_FUNCTION_DIS              BIT(15)
@@ -802,6 +804,11 @@ static void plda_pcie_hw_init(struct plda_pcie *pcie)
        value &= ~PMSG_LTR_SUPPORT;
        writel(value, pcie->reg_base + PMSG_SUPPORT_RX);
 
+       /* Prefetchable memory window 64-bit addressing support */
+       value = readl(pcie->reg_base + PCIE_WINROM);
+       value |= PREF_MEM_WIN_64_SUPPORT;
+       writel(value, pcie->reg_base + PCIE_WINROM);
+
        /* As the two host bridges in JH7110 soc have the same default
         * address translation table, this cause the second root port can't
         * access it's host bridge config space correctly.