net: mscc: ocelot: expose ocelot_pll5_init routine

Ocelot chips have an internal PLL that must be used when communicating
through external phys. Expose the init routine, so it can be used by other
drivers.

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c
index 08acb7b..9b8403e 100644 (file)
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -7,6 +7,7 @@
 #include <linux/dsa/ocelot.h>
 #include <linux/if_bridge.h>
 #include <linux/iopoll.h>
+#include <soc/mscc/ocelot_hsio.h>
 #include <soc/mscc/ocelot_vcap.h>
 #include "ocelot.h"
 #include "ocelot_vcap.h"
@@ -211,6 +212,36 @@ static void ocelot_mact_init(struct ocelot *ocelot)
        ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
 }
 
+void ocelot_pll5_init(struct ocelot *ocelot)
+{
+       /* Configure PLL5. This will need a proper CCF driver
+        * The values are coming from the VTSS API for Ocelot
+        */
+       regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
+                    HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
+                    HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
+       regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
+                    HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
+                    HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
+                    HSIO_PLL5G_CFG0_ENA_BIAS |
+                    HSIO_PLL5G_CFG0_ENA_VCO_BUF |
+                    HSIO_PLL5G_CFG0_ENA_CP1 |
+                    HSIO_PLL5G_CFG0_SELCPI(2) |
+                    HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
+                    HSIO_PLL5G_CFG0_SELBGV820(4) |
+                    HSIO_PLL5G_CFG0_DIV4 |
+                    HSIO_PLL5G_CFG0_ENA_CLKTREE |
+                    HSIO_PLL5G_CFG0_ENA_LANE);
+       regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
+                    HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
+                    HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
+                    HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
+                    HSIO_PLL5G_CFG2_ENA_AMPCTRL |
+                    HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
+                    HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
+}
+EXPORT_SYMBOL(ocelot_pll5_init);
+
 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
 {
        ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |

diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c
index 7388c3b..97e90e2 100644 (file)
--- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c
+++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c
@@ -18,7 +18,6 @@
 
 #include <soc/mscc/ocelot.h>
 #include <soc/mscc/ocelot_vcap.h>
-#include <soc/mscc/ocelot_hsio.h>
 #include <soc/mscc/vsc7514_regs.h>
 #include "ocelot_fdma.h"
 #include "ocelot.h"
@@ -26,35 +25,6 @@
 #define VSC7514_VCAP_POLICER_BASE                      128
 #define VSC7514_VCAP_POLICER_MAX                       191
 
-static void ocelot_pll5_init(struct ocelot *ocelot)
-{
-       /* Configure PLL5. This will need a proper CCF driver
-        * The values are coming from the VTSS API for Ocelot
-        */
-       regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
-                    HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
-                    HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
-       regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
-                    HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
-                    HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
-                    HSIO_PLL5G_CFG0_ENA_BIAS |
-                    HSIO_PLL5G_CFG0_ENA_VCO_BUF |
-                    HSIO_PLL5G_CFG0_ENA_CP1 |
-                    HSIO_PLL5G_CFG0_SELCPI(2) |
-                    HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
-                    HSIO_PLL5G_CFG0_SELBGV820(4) |
-                    HSIO_PLL5G_CFG0_DIV4 |
-                    HSIO_PLL5G_CFG0_ENA_CLKTREE |
-                    HSIO_PLL5G_CFG0_ENA_LANE);
-       regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
-                    HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
-                    HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
-                    HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
-                    HSIO_PLL5G_CFG2_ENA_AMPCTRL |
-                    HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
-                    HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
-}
-
 static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops)
 {
        int ret;

diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h
index 2080879..751d9b2 100644 (file)
--- a/include/soc/mscc/ocelot.h
+++ b/include/soc/mscc/ocelot.h
@@ -1183,4 +1183,6 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
 }
 #endif
 
+void ocelot_pll5_init(struct ocelot *ocelot);
+
 #endif