V4L2: clk and reset use bulk get
authorchanghuang.liang <changhuang.liang@starfivetech.com>
Mon, 25 Apr 2022 08:24:44 +0000 (16:24 +0800)
committerchanghuang.liang <changhuang.liang@starfivetech.com>
Tue, 26 Apr 2022 09:39:37 +0000 (17:39 +0800)
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
drivers/media/platform/starfive/v4l2_driver/stf_csi_hw_ops.c
drivers/media/platform/starfive/v4l2_driver/stf_vin_hw_ops.c
drivers/media/platform/starfive/v4l2_driver/stfcamss.c
drivers/media/platform/starfive/v4l2_driver/stfcamss.h

index ee8f5fa..cc6cbc0 100755 (executable)
@@ -80,12 +80,12 @@ static int stf_csi_clk_enable(struct stf_csi_dev *csi_dev)
     reg_set_bit(vin->clkgen_base, CLK_U0_VIN_CLK_P_AXIWR, BIT(24), 0x0<<24);
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rst);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rst);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rst);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rst);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rst);
-       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rst);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
+       reset_control_deassert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
 #else
     reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
                SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
@@ -106,12 +106,12 @@ static int stf_csi_clk_disable(struct stf_csi_dev *csi_dev)
        struct stfcamss *stfcamss = csi_dev->stfcamss;
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-       reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rst);
-       reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rst);
-       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rst);
-       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rst);
-       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rst);      
-       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rst);
+       reset_control_assert(stfcamss->sys_rst[STFRST_AXIWR].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_AXIRD].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF3].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF2].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF1].rstc);
+       reset_control_assert(stfcamss->sys_rst[STFRST_PIXEL_CLK_IF0].rstc);
 #else
     reg_assert_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
                SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
index df3a2ca..0c45597 100755 (executable)
@@ -106,12 +106,12 @@ static int stf_vin_clk_enable(struct stf_vin2_dev *vin_dev)
 
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_WRAPPER_C].rst);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_WRAPPER_P].rst);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_PCLK].rst);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_SYS_CLK].rst);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_AXIRD].rst);
-       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_AXIWR].rst);
+       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_WRAPPER_C].rstc);
+       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_WRAPPER_P].rstc);
+       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_PCLK].rstc);
+       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
+       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_AXIRD].rstc);
+       reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_AXIWR].rstc);
 #else
        reg_clear_rst(vin->clkgen_base, SOFTWARE_RESET_ASSERT0_ASSERT_SET,
                SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE,
@@ -151,10 +151,10 @@ static int stf_vin_clk_disable(struct stf_vin2_dev *vin_dev)
        struct stf_vin_dev *vin = vin_dev->stfcamss->vin;
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_PCLK].rst);
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_SYS_CLK].rst);
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_AXIRD].rst);
-       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_AXIWR].rst);
+       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_PCLK].rstc);
+       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_SYS_CLK].rstc);
+       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_AXIRD].rstc);
+       reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_AXIWR].rstc);
 #else
        reg_assert_rst(vin->clkgen_base,SOFTWARE_RESET_ASSERT0_ASSERT_SET,
                SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE, RSTN_U0_VIN_RST_N_PCLK
@@ -244,8 +244,8 @@ static void stf_vin_power_on(struct stf_vin2_dev *vin_dev,  int enable)
 #endif
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-               reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rst);
-               reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rst);
+               reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rstc);
+               reset_control_deassert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rstc);
 #else
                reg_clear_rst(vin->sys_crg, 0x2FCU, 0x30CU, (0x1 << 9));
                reg_clear_rst(vin->sys_crg, 0x2FCU, 0x30CU, (0x1 << 10));
@@ -254,8 +254,8 @@ static void stf_vin_power_on(struct stf_vin2_dev *vin_dev,  int enable)
        } else {
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rst);
-               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rst);
+               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_N].rstc);
+               reset_control_assert(vin_dev->stfcamss->sys_rst[STFRST_ISP_TOP_AXI].rstc);
 #else
                reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(9));
                reg_assert_rst(vin->sys_crg, 0x2FCU, 0x30cu, BIT(10));
index 9b5b91a..e745e2d 100755 (executable)
@@ -55,24 +55,24 @@ static const struct reg_name mem_reg_name[] = {
        {"syscrg"},
 };
 
-char *clocks[] = {
-       "clk_ispcore_2x",
-       "clk_isp_axi",
+static struct clk_bulk_data stfcamss_clocks[] = {
+       { .id = "clk_ispcore_2x" },
+       { .id = "clk_isp_axi" },
 };
 
-char *resets[] = {
-       "rst_isp_top_n",
-       "rst_isp_top_axi",
-       "rst_wrapper_p",
-       "rst_wrapper_c",
-       "rst_pclk",
-       "rst_sys_clk",
-       "rst_axird",
-       "rst_axiwr",
-       "rst_pixel_clk_if0",
-       "rst_pixel_clk_if1",
-       "rst_pixel_clk_if2",
-       "rst_pixel_clk_if3",
+static struct reset_control_bulk_data stfcamss_resets[] = {
+       { .id = "rst_isp_top_n" },
+       { .id = "rst_isp_top_axi" },
+       { .id = "rst_wrapper_p" },
+       { .id = "rst_wrapper_c" },
+       { .id = "rst_pclk" },
+       { .id = "rst_sys_clk" },
+       { .id = "rst_axird" },
+       { .id = "rst_axiwr" },
+       { .id = "rst_pixel_clk_if0" },
+       { .id = "rst_pixel_clk_if1" },
+       { .id = "rst_pixel_clk_if2" },
+       { .id = "rst_pixel_clk_if3" },
 };
 
 int stfcamss_get_mem_res(struct platform_device *pdev, struct stf_vin_dev *vin)
@@ -1035,47 +1035,22 @@ static int stfcamss_probe(struct platform_device *pdev)
        }
 
 #ifdef CONFIG_CLK_STARFIVE_JH7110
-       stfcamss->nclks = ARRAY_SIZE(clocks);
-       stfcamss->sys_clk = devm_kzalloc(dev, stfcamss->nclks * sizeof(*stfcamss->sys_clk),
-                       GFP_KERNEL);
-       if (!stfcamss->sys_clk) {
-               ret = -ENOMEM;
-               goto err_cam;
-       }
+       stfcamss->nclks = ARRAY_SIZE(stfcamss_clocks);
+       stfcamss->sys_clk = stfcamss_clocks;
 
-       for (i = 0; i < stfcamss->nclks; i++) {
-               struct stfcamss_clk *clock = &stfcamss->sys_clk[i];
-               clock->clk = devm_clk_get(dev, clocks[i]);
-               if (IS_ERR(clock->clk)) {
-                       st_err(ST_CAMSS, "get %s clocks name failed\n", clocks[i]);
-                       return PTR_ERR(clock->clk);
-               }
-               st_debug(ST_CAMSS, "get %s clocks name: \n", clocks[i]);
-
-               clock->name = clocks[i];
-       }
+       ret = devm_clk_bulk_get(dev, stfcamss->nclks, stfcamss->sys_clk);
+       if (ret)
+               st_err(ST_CAMSS, "faied to get clk controls\n");
 #endif
 
 #ifdef CONFIG_RESET_STARFIVE_JH7110
-       stfcamss->nrsts = ARRAY_SIZE(resets);
-       stfcamss->sys_rst = devm_kzalloc(dev, stfcamss->nrsts * sizeof(*stfcamss->sys_rst),
-                       GFP_KERNEL);
-       if (!stfcamss->sys_rst) {
-               ret = -ENOMEM;
-               goto err_cam;
-       }
+       stfcamss->nrsts = ARRAY_SIZE(stfcamss_resets);
+       stfcamss->sys_rst = stfcamss_resets;
 
-       for (i = 0; i < stfcamss->nrsts; i++) {
-               struct stfcamss_rst *reset = &stfcamss->sys_rst[i];
-               reset->rst = devm_reset_control_get_exclusive(dev, resets[i]);
-               if (IS_ERR(reset->rst)) {
-                       st_err(ST_CAMSS, "get %s resets name failed\n", resets[i]);
-                       return PTR_ERR(reset->rst);
-               }
-               st_debug(ST_CAMSS, "get %s resets name: \n", resets[i]);
-
-               reset->name = resets[i];
-       }
+       ret = devm_reset_control_bulk_get_exclusive(dev, stfcamss->nrsts,
+               stfcamss->sys_rst);
+       if (ret)
+               st_err(ST_CAMSS, "faied to get reset controls\n");
 #endif
 
        ret = stfcamss_get_mem_res(pdev, vin);
index f7aed67..39dd310 100755 (executable)
@@ -87,9 +87,9 @@ struct stfcamss {
        int isp_num;
        struct stf_isp_dev *isp_dev;   // subdev
        struct v4l2_async_notifier notifier;
-       struct stfcamss_clk *sys_clk;
+       struct clk_bulk_data *sys_clk;
        int nclks;
-       struct stfcamss_rst *sys_rst;
+       struct reset_control_bulk_data *sys_rst;
        int nrsts;
 #ifdef CONFIG_DEBUG_FS
        struct dentry *debugfs_entry;