imx: imx93_evk: Set ARM clock to 1.7Ghz
authorPeng Fan <peng.fan@nxp.com>
Tue, 26 Jul 2022 08:41:11 +0000 (16:41 +0800)
committerStefano Babic <sbabic@denx.de>
Tue, 26 Jul 2022 09:29:01 +0000 (11:29 +0200)
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/include/asm/arch-imx9/clock.h
arch/arm/mach-imx/imx9/clock.c
board/freescale/imx93_evk/spl.c

index d96f126..336d861 100644 (file)
@@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val);
 void dram_enable_bypass(ulong clk_val);
 void dram_disable_bypass(void);
 
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
 int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
 int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
 int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
@@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock
 void enable_usboh3_clk(unsigned char enable);
 int set_clk_enet(enum enet_freq type);
 int set_clk_eqos(enum enet_freq type);
-
+void set_arm_clk(ulong freq);
 #endif
index 11371f1..04f3116 100644 (file)
@@ -665,6 +665,15 @@ void dram_disable_bypass(void)
        /* Switch from DRAM  clock root from CCM to PLL */
        ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
 }
+
+void set_arm_clk(ulong freq)
+{
+       /* Increase ARM clock to 1.7Ghz */
+       ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+       configure_intpll(ARM_PLL_CLK, 1700000000);
+       ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
 #endif
 
 int clock_init(void)
index ca33f94..38cfbac 100644 (file)
@@ -108,6 +108,9 @@ void board_init_f(ulong dummy)
        }
        power_init_board();
 
+       /* 1.7GHz */
+       set_arm_clk(1700000000);
+
        /* Init power of mix */
        soc_power_init();