New PPC 405EP board added: CMS700

Added CONFIG_NET_MULTI for VOM405 board.
Added reset_phy() for VOM405 board.
Patch by Matthias Fuchs, 09 Nov 2005

diff --git a/CHANGELOG b/CHANGELOG
index 5747cb4..877df25 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* New PPC 405EP board added: CMS700
+  Added CONFIG_NET_MULTI for VOM405 board.
+  Added reset_phy() for VOM405 board.
+  Patch by Matthias Fuchs, 09 Nov 2005
+
 * Updated PCI mapping for esd CPCI2DP board.
   Add support for error LED.
   Patch by Matthias Fuchs, 07 Nov 2005

diff --git a/MAINTAINERS b/MAINTAINERS
index b889195..d026417 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -157,6 +157,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
        VOH405                  PPC405EP
        VOM405                  PPC405EP
        WUH405                  PPC405EP
+       CMS700                  PPC405EP
 
 Frank Gottschling <fgottschling@eltec.de>
 

diff --git a/MAKEALL b/MAKEALL
index 41892f8..903ab10 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -62,18 +62,18 @@ LIST_8xx="  \
 
 LIST_4xx="     \
        ADCIOP          AP1000          AR405           ASH405          \
-       bubinga         CANBT           CPCI2DP         CPCI405         \
-       CPCI4052        CPCI405AB       CPCI405DT       CPCI440         \
-       CPCIISER4       CRAYL1          csb272          csb472          \
-       DASA_SIM        DP405           DU405           ebony           \
-       ERIC            EXBITGEN        G2000           HH405           \
-       HUB405          JSE             KAREF           METROBOX        \
-       MIP405          MIP405T         ML2             ml300           \
-       ocotea          OCRTC           ORSG            PCI405          \
-       PIP405          PLU405          PMC405          PPChameleonEVB  \
-       sbc405          VOH405          W7OLMC          W7OLMG          \
-       walnut          WUH405          XPEDITE1K       yellowstone     \
-       yosemite        \
+       bubinga         CANBT           CMS700          CPCI2DP         \
+       CPCI405         CPCI4052        CPCI405AB       CPCI405DT       \
+       CPCI440         CPCIISER4       CRAYL1          csb272          \
+       csb472          DASA_SIM        DP405           DU405           \
+       ebony           ERIC            EXBITGEN        G2000           \
+       HH405           HUB405          JSE             KAREF           \
+       METROBOX        MIP405          MIP405T         ML2             \
+       ml300           ocotea          OCRTC           ORSG            \
+       PCI405          PIP405          PLU405          PMC405          \
+       PPChameleonEVB  sbc405          VOH405          VOM405          \
+       W7OLMC          W7OLMG          walnut          WUH405          \
+        XPEDITE1K      yellowstone     yosemite        \
 "
 
 #########################################################################

diff --git a/Makefile b/Makefile
index b91d5b8..1a9bdb1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -894,6 +894,9 @@ VOH405_config:      unconfig
 VOM405_config: unconfig
        @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd
 
+CMS700_config: unconfig
+       @./mkconfig $(@:_config=) ppc ppc4xx cms700 esd
+
 W7OLMC_config  \
 W7OLMG_config: unconfig
        @./mkconfig $(@:_config=) ppc ppc4xx w7o

diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
new file mode 100644 (file)
index 0000000..a11ee82
--- /dev/null
+++ b/board/esd/cms700/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+         ../common/xilinx_jtag/micro.o \
+         ../common/xilinx_jtag/ports.o
+
+OBJS   = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
new file mode 100644 (file)
index 0000000..649619d
--- /dev/null
+++ b/board/esd/cms700/cms700.c
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_early_init_f (void)
+{
+       /*
+        * IRQ 0-15  405GP internally generated; active high; level sensitive
+        * IRQ 16    405GP internally generated; active low; level sensitive
+        * IRQ 17-24 RESERVED
+        * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+        * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+        * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+        * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+        * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+        * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+        * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+        */
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(uicer, 0x00000000);       /* disable all ints */
+       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+       /*
+        * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+        */
+       mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+       /*
+        * Reset CPLD via GPIO12 (CS3) pin
+        */
+       out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+       udelay(1000); /* wait 1ms */
+       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+       udelay(1000); /* wait 1ms */
+
+       return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+       return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       /* adjust flash start and offset */
+       gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+       gd->bd->bi_flashoffset = 0;
+
+       /*
+        * Setup and enable EEPROM write protection
+        */
+       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+
+       /*
+        * Set NAND-FLASH GPIO signals to default
+        */
+       out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+       return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+       unsigned char str[64];
+       int flashcnt;
+       int delay;
+       volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
+       volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
+
+       puts ("Board: ");
+
+       if (getenv_r("serial#", str, sizeof(str))  == -1) {
+               puts ("### No HW ID - assuming CMS700");
+       } else {
+               puts(str);
+       }
+
+       printf(" (PLD-Version=%02d)\n", *ver_reg);
+
+       /*
+        * Flash LEDs
+        */
+       for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+               *led_reg = 0x00;        /* LEDs off */
+               for (delay = 0; delay < 100; delay++)
+                       udelay(1000);
+               *led_reg = 0x0f;        /* LEDs on */
+               for (delay = 0; delay < 50; delay++)
+                       udelay(1000);
+       }
+       *led_reg = 0x70;
+
+       return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+       unsigned long val;
+
+       mtdcr(memcfga, mem_mb0cf);
+       val = mfdcr(memcfgd);
+
+#if 0
+       printf("\nmb0cf=%x\n", val); /* test-only */
+       printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+       return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *                    0: disable write
+ *                    1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *                  0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+       if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+               return -1;
+       } else {
+               switch (state) {
+               case 1:
+                       /* Enable write access, clear bit GPIO_SINT2. */
+                       out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+                       state = 0;
+                       break;
+               case 0:
+                       /* Disable write access, set bit GPIO_SINT2. */
+                       out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+                       state = 0;
+                       break;
+               default:
+                       /* Read current status back. */
+                       state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+                       break;
+               }
+       }
+       return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       int query = argc == 1;
+       int state = 0;
+
+       if (query) {
+               /* Query write access state. */
+               state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+               if (state < 0) {
+                       puts ("Query of write access state failed.\n");
+               } else {
+                       printf ("Write access for device 0x%0x is %sabled.\n",
+                               CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+                       state = 0;
+               }
+       } else {
+               if ('0' == argv[1][0]) {
+                       /* Disable write access. */
+                       state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+               } else {
+                       /* Enable write access. */
+                       state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+               }
+               if (state < 0) {
+                       puts ("Setup of write access state failed.\n");
+               }
+       }
+
+       return state;
+}
+
+U_BOOT_CMD(eepwren,    2,      0,      do_eep_wren,
+          "eepwren - Enable / disable / query EEPROM write access\n",
+          NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+       nand_probe(CFG_NAND_BASE);
+       if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+               print_size(nand_dev_desc[0].totlen, "\n");
+       }
+}
+#endif
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+       /*
+        * Disable sleep mode in LXT971
+        */
+       lxt971_no_sleep();
+#endif
+}

diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk
new file mode 100644 (file)
index 0000000..5c3c01c
--- /dev/null
+++ b/board/esd/cms700/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CMS405 boards
+#
+
+TEXT_BASE = 0xFFFC0000

diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c
new file mode 100644 (file)
index 0000000..89af119
--- /dev/null
+++ b/board/esd/cms700/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+       unsigned long size_b0;
+       int i;
+       uint pbcr;
+       unsigned long base_b0;
+       int size_val = 0;
+
+       /* Init: no FLASHes known */
+       for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+               flash_info[i].flash_id = FLASH_UNKNOWN;
+       }
+
+       /* Static FLASH Bank configuration here - FIXME XXX */
+
+       size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+                       size_b0, size_b0<<20);
+       }
+
+       /* Setup offsets */
+       flash_get_offsets (-size_b0, &flash_info[0]);
+
+       /* Re-do sizing to get full correct info */
+       mtdcr(ebccfga, pb0cr);
+       pbcr = mfdcr(ebccfgd);
+       mtdcr(ebccfga, pb0cr);
+       base_b0 = -size_b0;
+       switch (size_b0) {
+       case 1 << 20:
+               size_val = 0;
+               break;
+       case 2 << 20:
+               size_val = 1;
+               break;
+       case 4 << 20:
+               size_val = 2;
+               break;
+       case 8 << 20:
+               size_val = 3;
+               break;
+       case 16 << 20:
+               size_val = 4;
+               break;
+       }
+       pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+       mtdcr(ebccfgd, pbcr);
+
+       /* Monitor protection ON by default */
+       (void)flash_protect(FLAG_PROTECT_SET,
+                           -CFG_MONITOR_LEN,
+                           0xffffffff,
+                           &flash_info[0]);
+
+       flash_info[0].size = size_b0;
+
+       return (size_b0);
+}

diff --git a/board/esd/cms700/fpgadata.c b/board/esd/cms700/fpgadata.c
new file mode 100644 (file)
index 0000000..08be5e7
--- /dev/null
+++ b/board/esd/cms700/fpgadata.c
@@ -0,0 +1,1812 @@
+  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
+  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
+  0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
+  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
+  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
+  0x08,0xea,0x08,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x00,0x24,0x00,0x1c,0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x00,0x28,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
+  0x00,0x14,0x00,0x61,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x00,0x00,0x03,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,
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+  0x01,0x09,0x00,0x35,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x35,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x35,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x35,0x28,0x00,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+  0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x00,
+  0x00,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x35,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+  0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x1c,
+  0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x14,0x00,0x61,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x35,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
+  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
+  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,

diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds
new file mode 100644 (file)
index 0000000..e672d08
--- /dev/null
+++ b/board/esd/cms700/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector layout of our flash chips!   XXX FIXME XXX   */
+
+    cpu/ppc4xx/start.o (.text)
+    cpu/ppc4xx/traps.o (.text)
+    cpu/ppc4xx/interrupts.o    (.text)
+    cpu/ppc4xx/serial.o        (.text)
+    cpu/ppc4xx/cpu_init.o      (.text)
+    cpu/ppc4xx/speed.o (.text)
+    common/dlmalloc.o  (.text)
+    lib_generic/crc32.o                (.text)
+    lib_ppc/extable.o  (.text)
+    lib_generic/zlib.o         (.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index 70bc6db..445b8fc 100644 (file)
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -79,12 +79,6 @@ int board_early_init_f (void)
 
 /* ------------------------------------------------------------------------- */
 
-int misc_init_f (void)
-{
-       return 0;  /* dummy implementation */
-}
-
-
 int misc_init_r (void)
 {
        DECLARE_GLOBAL_DATA_PTR;
@@ -132,11 +126,6 @@ int checkboard (void)
        }
        *led_reg = 0x40;
 
-       /*
-        * Disable sleep mode in LXT971
-        */
-       lxt971_no_sleep();
-
        return 0;
 }
 
@@ -159,10 +148,13 @@ long int initdram (int board_type)
 
 /* ------------------------------------------------------------------------- */
 
-int testdram (void)
+void reset_phy(void)
 {
-       /* TODO: XXX XXX XXX */
-       printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
 
-       return (0);
+       /*
+        * Disable sleep mode in LXT971
+        */
+       lxt971_no_sleep();
+#endif
 }

diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
new file mode 100644 (file)
index 0000000..6025886
--- /dev/null
+++ b/include/configs/CMS700.h
@@ -0,0 +1,393 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CMS700.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP           1       /* This is a PPC405 CPU         */
+#define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_VOM405          1       /* ...on a VOM405 board         */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
+#define CONFIG_MISC_INIT_R     1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ    33330000 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE                9600
+#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
+
+#undef CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#define CONFIG_PHY_ADDR                0       /* PHY address                  */
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
+                                CONFIG_BOOTP_DNS | \
+                                CONFIG_BOOTP_DNS2 | \
+                                CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_BSP     | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_NAND    | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_EEPROM  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
+
+#define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
+
+#undef  CONFIG_PRAM                    /* no "protected RAM"           */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+
+#undef CFG_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2    "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
+#else
+#define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_DEVICE_NULLDEV     1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET 1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+
+#undef CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59  /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD      691200
+#define        CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE     \
+       { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+        57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR  0x100000        /* default load address */
+#define CFG_EXTBDINFO  1               /* To use extended board_into (bd_t) */
+
+#define CFG_HZ         1000            /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1      /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER      16      /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR       0x68
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1) /* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0             /* configure as pci adapter     */
+#define PCI_HOST_FORCE 1               /* configure as pci host        */
+#define PCI_HOST_AUTO  2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_HOST  /* select pci host function     */
+#undef CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+                                       /* resource configuration       */
+
+#undef CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE      0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA 0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS 0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000     /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA 0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS 0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000     /* Host: use this pci address   */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM     0xFFC00000      /* FLASH bank #0        */
+
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip    */
+
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   1000    /* Timeout for Flash Write (in ms)      */
+
+#define CFG_FLASH_WORD_SIZE    unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0                0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1                0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0                0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1                0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2                0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK   0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS    1           /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_FLASH_BASE         0xFFFC0000
+#define CFG_MONITOR_BASE       TEXT_BASE
+#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (256 * 1024)    /* Reserve 256 kB for malloc()  */
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT           1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM   1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET         0x100   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE           0x700   /* 2048 bytes may be used for env vars*/
+                                  /* total size of a CAT24WC16 is 2048 bytes */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CFG_I2C_SPEED          100000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE          0x7F
+
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_I2C_EEPROM_ADDR_LEN 1      /* Bytes of address             */
+/* mask of address bits that overflow into the "EEPROM chip address"   */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
+                                       /* 16 byte page write mode using*/
+                                       /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_EEPROM_WREN         1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
+                                       /* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE     32      /* ...                  */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_PLD_BASE            0xf0000000
+#define CFG_NAND_BASE          0xF4000000  /* NAND FLASH Base Address          */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                      */
+#define CFG_EBC_PB0AP          0x92015480
+#define CFG_EBC_PB0CR          0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                     */
+#define CFG_EBC_PB1AP          0x92015480
+#define CFG_EBC_PB1CR          0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization             */
+#define CFG_EBC_PB2AP          0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR          0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL                1           /* using Xilinx XC95XL CPLD      */
+#define CFG_FPGA_MAX_SIZE      32*1024     /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG           0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK           0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA          0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT          0x00010000  /* unused (ppc input)            */
+#define CFG_FPGA_DONE          0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM       1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR      0xF8000000
+#define CFG_OCM_DATA_SIZE      0x1000
+#define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR /* inside of SDRAM            */
+#define CFG_INIT_RAM_END       CFG_OCM_DATA_SIZE /* End of used area in RAM    */
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]    - External Bus Controller BLAST output
+ * GPIO0[1-9]  - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:         OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:                OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CFG_GPIO0_OSRH         0x40000500  /*  0 ... 15 */
+#define CFG_GPIO0_OSRL         0x00000110  /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H                0x00000000  /*  0 ... 15 */
+#define CFG_GPIO0_ISR1L                0x14000045  /* 16 ... 31 */
+#define CFG_GPIO0_TSRH         0x00000000  /*  0 ... 15 */
+#define CFG_GPIO0_TSRL         0x00000000  /* 16 ... 31 */
+#define CFG_GPIO0_TCR          0xF7FE0014  /*  0 ... 31 */
+
+#define CFG_EEPROM_WP          (0x80000000 >> 8)    /* GPIO8 */
+#define CFG_PLD_RESET          (0x80000000 >> 12)   /* GPIO12 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT  PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT  PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT  PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT  PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT  PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT  PLLMR1_133_66_66_33
+#endif
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 64b6c53..f2f3ea7 100644 (file)
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -52,9 +52,13 @@
 
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
+
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
                                 CONFIG_BOOTP_DNS | \